摘要:
Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
摘要:
Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
摘要:
Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
摘要:
A semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
摘要:
Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
摘要:
Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
摘要:
In accordance with one aspect of the present description, a transmission line such as a microstrip or stripline transmission line, has stub-shaped projections adapted to compensate simultaneously for both far-end crosstalk (FEXT) induced by inductive coupling between the transmission line and an adjacent transmission line, and also far-end crosstalk induced by inductive coupling between the vertical electrical interconnect at the far end of the transmission line and an adjacent vertical electrical interconnect electrically connected to the adjacent transmission line. In another aspect of the present description, a microstrip transmission line may have multiple stubby line sections having different resistances and impedances to more gradually transition from to the typically low impedance characteristics of vertical interconnects such as the PTH vias and socket connectors. Other aspects are described.
摘要:
In accordance with one aspect of the present description, a transmission line such as a microstrip or stripline transmission line, has stub-shaped projections adapted to compensate simultaneously for both far-end crosstalk (FEXT) induced by inductive coupling between the transmission line and an adjacent transmission line, and also far-end crosstalk induced by inductive coupling between the vertical electrical interconnect at the far end of the transmission line and an adjacent vertical electrical interconnect electrically connected to the adjacent transmission line. In another aspect of the present description, a microstrip transmission line may have multiple stubby line sections having different resistances and impedances to more gradually transition from to the typically low impedance characteristics of vertical interconnects such as the PTH vias and socket connectors. Other aspects are described.