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公开(公告)号：US09910824B2
公开(公告)日：2018-03-06
申请号：US14727076
申请日：2015-06-01
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that separate a vector or combine two vectors. The computer processor may be implemented as a monolithic integrated circuit.
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公开(公告)号：US10733140B2
公开(公告)日：2020-08-04
申请号：US14727051
申请日：2015-06-01
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Arthur Joseph Hoane , Paul Hurtley
Abstract: A computer processor is disclosed. The computer processor may comprises a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that produce results with elements of widths different than that of the input elements. The computer processor may be implemented as a monolithic integrated circuit.
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3.发明申请VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING ONE OR MORE COMPLEX ARITHMETIC INSTRUCTIONS 审中-公开使用一个或多个复杂算术指令配置在可变长度向量上运行的矢量处理器公开(公告)号：US20160224340A1
公开(公告)日：2016-08-04
申请号：US14724061
申请日：2015-05-28
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Sitij Agrawal
IPC: G06F9/30
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F9/461 , G06F9/462 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more complex arithmetic instructions. The computer processor may be implemented as a monolithic integrated circuit.
Abstract translation: 公开了一种计算机处理器。 计算机处理器可以包括向量单元，其包括向量寄存器文件，其包括至少一个寄存器以保存不同数量的元件。 计算机处理器还可以包括处理逻辑，其被配置为使用一个或多个复数运算指令对矢量寄存器堆中的变化数量的元件进行操作。 计算机处理器可以被实现为单片集成电路。
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4.发明授权公开(公告)号：US10922267B2
公开(公告)日：2021-02-16
申请号：US14718432
申请日：2015-05-21
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Vitaly Kalashnikov , Sitij Agrawal
Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more graphics processing instructions. The computer processor may be implemented as a monolithic integrated circuit.
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公开(公告)号：US20160364236A1
公开(公告)日：2016-12-15
申请号：US15155570
申请日：2016-05-16
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan
IPC: G06F9/30
CPC classification number: G06F9/30189 , G06F9/3005 , G06F9/30145 , G06F9/3851 , G06F9/462
Abstract: A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include witching mode logic to switch between the first mode and the second mode.
Abstract translation: 计算机处理器可以包括多个硬件线程。 计算机处理器还可以包括用于硬件线程的状态的状态处理器逻辑。 状态处理器逻辑可以包括每个线程逻辑，其包含在多个硬件线程的每个硬件线程中被复制的状态和独立于多个硬件线程中的每个硬件线程的公共逻辑。 计算机处理器还可以包括单线程模式逻辑，以仅从多个硬件线程中的一个硬件线程以单线程模式执行指令。 计算机处理器还可以包括第二模式逻辑，用于同时执行来自多个硬件线程的多于一个硬件线程的第二模式的指令。 计算机处理器还可以包括在第一模式和第二模式之间切换的巫师模式逻辑。
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Patent Agency Ranking
公开(公告)号：US10824586B2
公开(公告)日：2020-11-03
申请号：US14724061
申请日：2015-05-28
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Sitij Agrawal
Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more complex arithmetic instructions. The computer processor may be implemented as a monolithic integrated circuit.
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公开(公告)号：US09959246B2
公开(公告)日：2018-05-01
申请号：US14728522
申请日：2015-06-02
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Vitaly Kalashnikov
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor may further comprise processing logic configured to implicitly type each of the varying number of elements in the vector register file. The computer processor may be implemented as a monolithic integrated circuit.
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8.发明申请VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS WITH REGISTER RENAMING 审中-公开矢量处理器被配置为在具有寄存器恢复功能的可变长度矢量上运行公开(公告)号：US20160224514A1
公开(公告)日：2016-08-04
申请号：US14719432
申请日：2015-05-22
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , Arthur Joseph Hoane
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F9/461 , G06F9/462 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor comprises a vector unit comprising a vector register file comprising at least one vector register to hold a varying number of elements. The number of architected vector registers in the vector register file differs from the number of physical vector registers in the vector register file.
Abstract translation: 公开了一种计算机处理器。 计算机处理器包括矢量单元，其包括矢量寄存器文件，该矢量寄存器文件包括至少一个矢量寄存器以保存不同数量的元件。 向量寄存器文件中的架构向量寄存器数量与向量寄存器文件中物理向量寄存器的数量不同。
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9.发明申请VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING GRAPHICS PROCESSING INSTRUCTIONS 审中-公开使用图形处理指令配置可变长度矢量图的矢量处理器公开(公告)号：US20160224510A1
公开(公告)日：2016-08-04
申请号：US14718432
申请日：2015-05-21
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Vitaly Kalashnikov , Sitij Agrawal
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F9/461 , G06F9/462 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more graphics processing instructions. The computer processor may be implemented as a monolithic integrated circuit.
Abstract translation: 公开了一种计算机处理器。 计算机处理器可以包括向量单元，其包括向量寄存器文件，其包括至少一个寄存器以保存不同数量的元件。 计算机处理器还可以包括处理逻辑，其被配置为使用一个或多个图形处理指令对向量寄存器堆中的变化数量的元件进行操作。 计算机处理器可以被实现为单片集成电路。
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10.发明授权公开(公告)号：US11544214B2
公开(公告)日：2023-01-03
申请号：US14709730
申请日：2015-05-12
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola , Vitaly Kalashnikov , Sitij Agrawal
Abstract: A computer processor comprising a vector unit is disclosed. The vector unit may comprise a vector register file comprising at least one register to hold a varying number of elements. The vector unit may further comprise a vector length register file comprising at least one register to specify the number of operations of a vector instruction to be performed on the varying number of elements in the at least one register of the vector register file. The computer processor may be implemented as a monolithic integrated circuit.
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