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1.发明申请公开(公告)号：US20160314074A1
公开(公告)日：2016-10-27
申请号：US15087150
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
CPC classification number: G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
Abstract: A computer processor that implements pre-translation of virtual addresses is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual address, the virtual address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.
Abstract translation: 公开了实现虚拟地址的预翻译的计算机处理器。 计算机处理器可以包括包括一个或多个寄存器的寄存器文件。 计算机处理器可以包括处理逻辑。 处理逻辑可以接收一个值以存储在一个或多个寄存器的寄存器中。 处理逻辑可以将该值存储在寄存器中。 处理逻辑可以将接收的值指定为虚拟地址，虚拟地址具有对应的虚拟基页号。 处理逻辑可以将虚拟基页编号转换为对应的真实基页编号和对应于与虚拟基页编号相邻的零个或多个虚拟页码的零个或多个实际页号。 处理逻辑还可以在一个或多个寄存器的寄存器中存储真实的基页号码和零个或多个实际页码。
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公开(公告)号：US10169039B2
公开(公告)日：2019-01-01
申请号：US15087150
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC: G06F12/08 , G06F12/10 , G06F9/30 , G06F3/06 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F12/0862 , G06F9/32 , G06F9/355
Abstract: A computer processor that implements pre-translation of virtual addresses is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual address, the virtual address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.
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3.发明申请COMPUTER PROCESSOR WITH REGISTER DIRECT BRANCHES AND EMPLOYING AN INSTRUCTION PRELOAD STRUCTURE 有权具有注册直接分支机构的计算机处理器，并采用指令性预告结构公开(公告)号：US20160314071A1
公开(公告)日：2016-10-27
申请号：US15087269
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
CPC classification number: G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
Abstract: A computer processor with register direct branches and employing an instruction preload structure is disclosed. The computer processor may include a hierarchy of memories comprising a first memory organized in a structure having one or more entries for one or more addresses corresponding to one or more instructions. The one or more entries of the one or more addresses may have a starting address. The structure may have one or more locations for storing the one or more instructions. The computer processor may include one or more registers to which one or more corresponding instruction addresses are writable. The computer processor may include processing logic. In response to the processing logic writing the one or more instruction addresses to the one or more registers, the processing logic may to pre-fetch the one or more instructions of a linear sequence of instructions from a first memory level of the hierarchy of memories into a second memory level of the hierarchy of memories beginning at the starting address. At least one address of the one or more addresses may be the contents of a register of the one or more registers.
Abstract translation: 公开了一种具有寄存器直接分支和采用指令预加载结构的计算机处理器。 计算机处理器可以包括存储器层级，其包括以具有一个或多个对应于一个或多个指令的地址的一个或多个地址的一个或多个条目的结构组织的第一存储器。 一个或多个地址的一个或多个条目可以具有起始地址。 该结构可以具有用于存储一个或多个指令的一个或多个位置。 计算机处理器可以包括一个或多个寄存器，一个或多个对应的指令地址可写入到该寄存器。 计算机处理器可以包括处理逻辑。 响应于将一个或多个指令地址写入一个或多个寄存器的处理逻辑，处理逻辑可以从存储器层级的第一存储器级别预先获取线性指令序列的一个或多个指令， 从起始地址开始的存储器层级的第二存储器级别。 一个或多个地址的至少一个地址可以是一个或多个寄存器的寄存器的内容。
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4.发明授权公开(公告)号：US09940129B2
公开(公告)日：2018-04-10
申请号：US15087269
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC: G06F12/08 , G06F9/30 , G06F3/06 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F12/0862 , G06F9/32 , G06F9/355
CPC classification number: G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
Abstract: A computer processor with register direct branches and employing an instruction preload structure is disclosed. The computer processor may include a hierarchy of memories comprising a first memory organized in a structure having one or more entries for one or more addresses corresponding to one or more instructions. The one or more entries of the one or more addresses may have a starting address. The structure may have one or more locations for storing the one or more instructions. The computer processor may include one or more registers to which one or more corresponding instruction addresses are writable. The computer processor may include processing logic. In response to the processing logic writing the one or more instruction addresses to the one or more registers, the processing logic may to pre-fetch the one or more instructions of a linear sequence of instructions from a first memory level of the hierarchy of memories into a second memory level of the hierarchy of memories beginning at the starting address. At least one address of the one or more addresses may be the contents of a register of the one or more registers.
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公开(公告)号：US09910824B2
公开(公告)日：2018-03-06
申请号：US14727076
申请日：2015-06-01
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that separate a vector or combine two vectors. The computer processor may be implemented as a monolithic integrated circuit.
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Patent Agency Ranking
公开(公告)号：US12050910B2
公开(公告)日：2024-07-30
申请号：US17427832
申请日：2020-02-20
Applicant: Optimum Semiconductor Technologies Inc.
Inventor： Mayan Moudgill , Pablo Balzola , Murugappan Senthivelan , Vaidyanathan Ramdurai , Sitij Agrawal
CPC classification number: G06F9/3001 , G06F7/5446 , G06F7/548 , G06F9/3013 , G06F17/17 , G06F5/01
Abstract: A system and an accelerator circuit including a register file comprising instruction registers to store a trigonometric calculation instruction for evaluating a trigonometric function, and data registers comprising a first data register to store a floating-point input value associated with the trigonometric calculation instruction. The accelerator circuit further includes a determination circuit to identify the trigonometric calculation function and the floating-point input value associated with the trigonometric calculation instruction and determine whether the floating-point input value is in a small value range, and an approximation circuit to responsive to determining that the floating-point input value is in the small value, receive the floating-point input value and calculate an approximation of the trigonometric function with respect to the input value.
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7.发明授权公开(公告)号：US11928465B2
公开(公告)日：2024-03-12
申请号：US17427843
申请日：2020-02-20
Applicant: Optimum Semiconductor Technologies Inc.
Inventor： Mayan Moudgill , Pablo Balzola , Murugappan Senthivelan , Vaidyanathan Ramdurai , Sitij Agrawal
CPC classification number: G06F9/3001 , G06F7/5446 , G06F7/548 , G06F9/3013 , G06F17/17 , G06F5/01
Abstract: A system and an accelerator circuit including a register file comprising instruction registers to store an instruction for evaluating an elementary function, and data registers comprising a first data register to store an input value. The accelerator circuit further includes a successive cumulative rotation circuit comprising a reconfigurable inner stage to perform a successive cumulative rotation recurrence, and a determination circuit to determine a type of the elementary function based on the instruction, and responsive to determining that the input value is a fixed-point number, configure the reconfigurable inner stage to a configuration for evaluating the type of the elementary function, wherein the successive cumulative rotation circuit is to calculate an evaluation of the elementary function using the reconfigurable inner stage performing the successive cumulative rotation recurrence.
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公开(公告)号：US20180173527A1
公开(公告)日：2018-06-21
申请号：US15841959
申请日：2017-12-14
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola , Vaidyanathan Thevangudi Ramadurai
IPC: G06F9/30
Abstract: A processor including a first storage to store a first data item, a second storage, and an execution unit comprising a logic circuit encoding an instruction, the instruction comprising a first field to store an identifier of the first storage, a second field to store an identifier of the second storage, and a third field to store an identifier representing a rounding rule, wherein the execution unit is to execute the instruction to generate a second data item based on the first data item, round the second data item according to the rounding rule specified by the instruction, and store the rounded second data item in the second storage.
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公开(公告)号：US20160313996A1
公开(公告)日：2016-10-27
申请号：US15086711
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
Abstract: A computer processor with an address register file is disclosed. The computer processor may include a memory. The computer processor may further include a general purpose register file comprising at least one general purpose register. The computer processor may further include an address register file comprising at least one address register. The computer processor may further include having access to the memory, the general purpose register file, and the address register file. The processing logic may execute a memory access instruction that accesses one or more memory locations in the memory at one or more corresponding addresses computed by retrieving the value of an address register of the at least one register of the address register file specified in the instruction and adding a displacement value encoded in the instruction.
Abstract translation: 公开了一种具有地址寄存器文件的计算机处理器。 计算机处理器可以包括存储器。 计算机处理器还可以包括包括至少一个通用寄存器的通用寄存器文件。 计算机处理器还可以包括包括至少一个地址寄存器的地址寄存器文件。 计算机处理器还可以包括访问存储器，通用寄存器文件和地址寄存器文件。 处理逻辑可以执行存储器访问指令，该存储器访问指令通过检索指令中指定的地址寄存器文件的至少一个寄存器的地址寄存器的值而计算的一个或多个对应地址访问存储器中的一个或多个存储器位置，以及 添加在指令中编码的位移值。
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公开(公告)号：US20160313995A1
公开(公告)日：2016-10-27
申请号：US15086752
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC: G06F9/30
CPC classification number: G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F12/1027 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/6028 , G06F2212/651 , G06F2212/684
Abstract: A computer processor with indirect only branching is disclosed. The computer processor may include one or more target registers. The computer processor may include processing logic in signal communication with the one or more target registers. The processing logic may execute a non-interrupting branch instruction based on a value stored in a target register of the one or more target registers. The non-interrupting branch instruction may use the one or more target registers to specify a destination address of a branch specified by the non-interrupting branch instruction.
Abstract translation: 公开了一种仅间接分支的计算机处理器。 计算机处理器可以包括一个或多个目标寄存器。 计算机处理器可以包括与一个或多个目标寄存器进行信号通信的处理逻辑。 处理逻辑可以基于存储在一个或多个目标寄存器的目标寄存器中的值来执行非中断分支指令。 非中断分支指令可以使用一个或多个目标寄存器来指定由非中断分支指令指定的分支的目的地地址。
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