公开(公告)号：US20190324939A1

公开(公告)日：2019-10-24

申请号：US16457793

申请日：2019-06-28

Applicant: Oracle International Corporation

Inventor： David A. Brown ,  Daniel Fowler ,  Rishabh Jain ,  Erik Schlanger ,  Michael Duller

IPC: G06F13/42 ,  G06F1/3234

Abstract: Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

公开(公告)号：US20180067889A1

公开(公告)日：2018-03-08

申请号：US15256936

申请日：2016-09-06

Applicant: Oracle International Corporation

Inventor： David A. Brown ,  Daniel Fowler ,  Rishabh Jain ,  Erik Schlanger ,  Michael Duller

IPC: G06F13/42 ,  G06F1/32

CPC classification number: G06F13/4221 ,  G06F1/3243 ,  Y02D10/152

Abstract: Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

公开(公告)号：US20180107482A1

公开(公告)日：2018-04-19

申请号：US15296886

申请日：2016-10-18

Applicant: Oracle International Corporation

Inventor： Erik Schlanger ,  Charles Roth ,  Daniel Fowler

IPC: G06F9/34 ,  G06F9/30

CPC classification number: G06F9/30021 ,  G06F9/30 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/345

Abstract: Circuitry may be configured to identify a particular element position of a bit vector stored in a register, where a value of the element occupying the particular element position matches a first predetermined value, and determine an address value dependent upon the particular element position of the bit vector and a base address. The circuitry may be further configured to load data from a memory dependent upon the address value.

公开(公告)号：US10380058B2

公开(公告)日：2019-08-13

申请号：US15256936

申请日：2016-09-06

Applicant: Oracle International Corporation

Inventor： David A. Brown ,  Daniel Fowler ,  Rishabh Jain ,  Erik Schlanger ,  Michael Duller

IPC: G06F13/42 ,  G06F1/3234 ,  G06F1/32

Abstract: Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

公开(公告)号：US20190187988A1

公开(公告)日：2019-06-20

申请号：US16284666

申请日：2019-02-25

Applicant: Oracle International Corporation

Inventor： Erik Schlanger ,  Charles Roth ,  Daniel Fowler

IPC: G06F9/30 ,  G06F9/345

CPC classification number: G06F9/30021 ,  G06F9/30 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/345

Abstract: Circuitry may be configured to identify a particular element position of a bit vector stored in a register, where a value of the element occupying the particular element position matches a first predetermined value, and determine an address value dependent upon the particular element position of the bit vector and a base address. The circuitry may be further configured to load data from a memory dependent upon the address value.

公开(公告)号：US10216515B2

公开(公告)日：2019-02-26

申请号：US15296886

申请日：2016-10-18

Applicant: Oracle International Corporation

Inventor： Erik Schlanger ,  Charles Roth ,  Daniel Fowler

IPC: G06F9/30 ,  G06F9/345

Abstract: Circuitry may be configured to identify a particular element position of a bit vector stored in a register, where a value of the element occupying the particular element position matches a first predetermined value, and determine an address value dependent upon the particular element position of the bit vector and a base address. The circuitry may be further configured to load data from a memory dependent upon the address value.