公开(公告)号：US20200174875A1

公开(公告)日：2020-06-04

申请号：US16204615

申请日：2018-11-29

Applicant: Oracle International Corporation

Inventor： David Rudy ,  Robert Hueston ,  Scott Cooke ,  Paul Mitchell

IPC: G06F11/07

Abstract: Utilities (e.g., systems, methods, etc.) that make use of a secure input/output (I/O) channel between system firmware (e.g., BIOS) and the SP to allow the BIOS to securely send data (e.g., error data) for secure consumption by the SP while preventing or limiting other sources from sending falsified data or the like the SP. The secure I/O channel includes interface hardware (e.g., Field-programmable gate array (FPGA)) that is configured to be unlocked by the BIOS using a security key received from a key generator over a separate security channel. After such data is securely sent to the interface hardware, the BIOS may then pass error interrupt(s) to the OS for performing of any necessary recovery actions. At any appropriate time, the SP may read or consume error data from the memory register of the interface hardware and perform any appropriate diagnoses and/or handling of the error data.

公开(公告)号：US10656205B2

公开(公告)日：2020-05-19

申请号：US15886566

申请日：2018-02-01

Applicant: Oracle International Corporation

Inventor： Mark Semmelmeyer ,  Ali Vahidsafa ,  Sebastian Turullols ,  Scott Cooke ,  Senthilkumar Diraviam ,  Preethi Sama

IPC: G01R31/3183 ,  G01R31/28 ,  G01R31/319 ,  G01R31/317

Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.