公开(公告)号：US5892979A

公开(公告)日：1999-04-06

申请号：US967219

申请日：1997-10-29

申请人： Osamu Shiraki ,  Yoichi Koyanagi ,  Takeshi Horie ,  Toshiyuki Shimizu ,  Hiroaki Ishihata

发明人： Osamu Shiraki ,  Yoichi Koyanagi ,  Takeshi Horie ,  Toshiyuki Shimizu ,  Hiroaki Ishihata

IPC分类号： G11C7/00 ,  G06F5/06 ,  G06F13/00

CPC分类号： G06F5/06

摘要： An overflow control unit stores, in a FIFO buffer, data generated by a processor. The overflow control unit sets a predetermined flag, upon detecting that a FIFO buffer is full or nearly full. The overflow control unit stores, in a saving buffer, data sent from the processor, while the flag is set. Thereafter, the overflow control unit notifies the processor, by an interrupt, of an effect that an available capacity of the FIFO buffer rises above a predetermined threshold.Upon receiving an interrupt, the processor transfers to the FIFO buffer data saved in the saving buffer. Upon a completion of transferring to the FIFO buffer all data saved in the saving buffer, the processor resets the flag. This allows the overflow control unit to again store in the FIFO buffer, data sent from the processor. The overflow control unit also monitors the volume of data stored in the saving buffer, and notifies the processor, by an interrupt, of an effect that the saving buffer is full. Upon receiving an interrupt, the processor expands an available capacity of the saving buffer.

摘要翻译： 溢出控制单元在FIFO缓冲器中存储由处理器生成的数据。 检测到FIFO缓冲器已满或接近满时，溢出控制单元设置预定标志。 在保存缓冲器中，溢出控制单元在设置标志时存储从处理器发送的数据。 此后，溢出控制单元通过中断通知处理器FIFO缓冲器的可用容量上升到预定阈值以上的效果。 在接收到中断时，处理器将传输到保存在保存缓冲区中的FIFO缓冲区数据。 在完成向FIFO缓冲区传送保存在保存缓冲区中的所有数据后，处理器重置标志。 这允许溢出控制单元再次存储在FIFO缓冲器中，从处理器发送的数据。 溢出控制单元还监视存储在保存缓冲器中的数据量，并通过中断向处理器通知保存缓冲器已满的效果。 在接收到中断时，处理器扩展了保存缓冲区的可用容量。

公开(公告)号：US5742843A

公开(公告)日：1998-04-21

申请号：US503916

申请日：1995-07-19

申请人： Yoichi Koyanagi ,  Osamu Shiraki ,  Takeshi Horie ,  Toshiyuki Shimizu ,  Hiroaki Ishihata

发明人： Yoichi Koyanagi ,  Osamu Shiraki ,  Takeshi Horie ,  Toshiyuki Shimizu ,  Hiroaki Ishihata

IPC分类号： G06F15/17 ,  G06F15/80

CPC分类号： G06F15/17

摘要： When the processor writes a command data string into an address of the command entry area, a corresponding command is created by a bus interface. If an address output by the processor corresponds to a distributed shared memory area, the bus interface creates a remote access command. The send controller constructs a message based on the command created by the bus interface. This message is sent either to an interconnection network, or to a receive controller. The receive controller receives the message and interprets it. An address output by the processor is detected by a cache area access unit, and the cache area in the memory is accessed. When the processor receives an interrupt request while waiting for a response message to a remote read request, an deadlock control unit detects an abnormal end of the remote read request that the remote read has ended in an error, and, controls the processor to process the interrupt request with priority.

摘要翻译： 当处理器将命令数据串写入命令输入区域的地址时，由总线接口创建相应的命令。 如果处理器输出的地址对应于分布式共享存储器区域，则总线接口创建远程访问命令。 发送控制器根据总线接口创建的命令构建消息。 该消息被发送到互连网络或发送到接收控制器。 接收控制器接收消息并对其进行解释。 由处理器输出的地址由高速缓存区域访问单元检测，存储器中的高速缓存区域被访问。 当处理器在等待对远程读取请求的响应消息的同时接收到中断请求时，死锁控制单元检测到远程读取已经结束的远程读取请求的异常结束，并且控制处理器 中断请求优先。

公开(公告)号：US6115803A

公开(公告)日：2000-09-05

申请号：US10627

申请日：1998-01-22

申请人： Kenichi Hayashi ,  Yoichi Koyanagi ,  Takeshi Horie ,  Osamu Shiraki

发明人： Kenichi Hayashi ,  Yoichi Koyanagi ,  Takeshi Horie ,  Osamu Shiraki

IPC分类号： G06F15/17 ,  G06F9/46 ,  G06F9/54 ,  G06F15/163 ,  G06F15/177 ,  G06F9/345 ,  G06F9/38

CPC分类号： G06F9/54

摘要： A parallel computer including a plurality of processing elements, each of processing elements comprising a flag address holding unit for temporarily holding an address of a send complete flag of a direct remote write message when the direct remote write message is sent to another processing element, and a flag update unit for exclusively updating a flag represented by the address held in the flag address holding unit when data indicated by the direct remote write message has been sent.

摘要翻译： 一种并行计算机，包括多个处理元件，每个处理元件包括标志地址保持单元，用于当直接远程写入消息被发送到另一个处理元件时临时保存直接远程写入消息的发送完成标志的地址;以及 标志更新单元，用于当已经发送由直接远程写入消息指示的数据时，专门地更新由保持在标志地址保持单元中的地址表示的标志。

公开(公告)号：US5928351A

公开(公告)日：1999-07-27

申请号：US764109

申请日：1996-12-06

申请人： Takeshi Horie ,  Masaaki Nagatsuka ,  Kenichi Kobayashi ,  Osamu Shiraki

发明人： Takeshi Horie ,  Masaaki Nagatsuka ,  Kenichi Kobayashi ,  Osamu Shiraki

IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F15/177 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F9/52

摘要： A parallel computer system capable of arbitrarily selecting nodes participating in barrier synchronization while enabling an arbitrary number of node groups to independently execute a process requiring the barrier synchronization. A communication network for the parallel computer system includes a plurality of routing controllers. Each routing controller has a register for setting a predetermined number of receipts of barrier synchronization request messages from other routing controllers, a destination to which the barrier synchronization request message is transmitted, and a destination to which a barrier synchronization establishment message is transmitted. If a destination of transmission of the barrier synchronization request message is set when completing a predetermined number of receipts of the barrier synchronization request messages and receipts of a barrier synchronization request message from a self-node, the barrier synchronization request message is transmitted to that destination of transmission. If the transmission destination is not set, the barrier synchronization establishment message is transmitted to the set transmission destination of the barrier synchronization establishment message. When receiving the barrier synchronization establishment message, the barrier synchronization establishment message is also transmitted to the set transmission destination of the barrier synchronization establishment message.

摘要翻译： 一种并行计算机系统，其能够任意选择参与屏障同步的节点，同时允许任意数量的节点组独立地执行需要屏障同步的过程。 并行计算机系统的通信网络包括多个路由控制器。 每个路由控制器具有用于设置来自其他路由控制器的屏障同步请求消息的预定数量的接收的寄存器，发送屏障同步请求消息的目的地和发送屏障同步建立消息的目的地。 如果在完成屏障同步请求消息的预定数量的接收和来自自身节点的屏障同步请求消息的接收时设置了屏障同步请求消息的发送目的地，则将该屏障同步请求消息发送到该目的地 的传输。 如果未设置发送目的地，则将障碍同步建立消息发送到屏障同步建立消息的设定发送目的地。 当接收到屏障同步建立消息时，屏障同步建立消息也被发送到屏障同步建立消息的设置发送目的地。

公开(公告)号：US09712430B2

公开(公告)日：2017-07-18

申请号：US13596165

申请日：2012-08-28

申请人： Osamu Shiraki

发明人： Osamu Shiraki

IPC分类号： H04L12/28 ,  H04L12/721 ,  H04L12/935

CPC分类号： H04L45/38 ,  H04L49/3009

摘要： A relay apparatus includes a first data storage unit and a processor. The first data storage unit stores an output port identifier in connection with a combination of a port identifier and a communication type identifier. The processor obtains, when a frame is received, a first output port identifier corresponding to a combination of a port identifier of a port that received the frame and a communication type identifier included in the received frame by use of the first data storage unit to output the received frame to a port identified by the first output port identifier.

公开(公告)号：US20130107890A1

公开(公告)日：2013-05-02

申请号：US13610168

申请日：2012-09-11

申请人： Kazuki HYOUDOU ,  Osamu Shiraki

发明人： Kazuki HYOUDOU ,  Osamu Shiraki

IPC分类号： H04L12/56

CPC分类号： H04L47/17 ,  H04B7/155 ,  H04L47/24 ,  H04L47/30 ,  H04L47/32

摘要： There is provided a relay device including: a buffer configured to store a received frame; a discarding unit configured to discard the received frame, when a utilization amount of the buffer exceeds a first value set corresponding to a communication type of the received frame; a first calculating unit configured to calculate the utilization amount of the buffer for each communication type at least two points in time, and calculate an amount of change in the utilization amount of the buffer for each communication type; and a setting unit configured to calculate the first value for each communication type, based on the amount of change in the utilization amount, and set the first value in the discarding unit.

摘要翻译： 提供了一种中继装置，包括：缓冲器，被配置为存储接收到的帧; 当所述缓冲器的使用量超过与接收到的帧的通信类型相对应的第一值集时，丢弃所述接收到的帧; 第一计算单元，被配置为在至少两个时间点计算每种通信类型的缓冲器的使用量，并且计算每种通信类型的缓冲器的使用量的变化量; 以及设置单元，被配置为基于利用量的变化量来计算每个通信类型的第一值，并且设置丢弃单元中的第一值。

公开(公告)号：US20100316057A1

公开(公告)日：2010-12-16

申请号：US12801371

申请日：2010-06-04

申请人： Osamu Shiraki ,  Takeshi Shimizu

发明人： Osamu Shiraki ,  Takeshi Shimizu

IPC分类号： H04L12/56

CPC分类号： H04L49/25 ,  H04L45/18 ,  H04L49/552 ,  H04L49/65

摘要： In a relay device, a first memory stores correspondence information representing a correspondence relationship between a node and a port. A second memory stores information by which a port to suppress flooding of a frame is distinguishable. A relay part limits a port, which floods a frame addressed to a node of which information is not stored in the first memory, based on the information stored in the second memory.

摘要翻译： 在中继装置中，第一存储器存储表示节点和端口之间的对应关系的对应信息。 第二存储器存储用于抑制框架的泛洪的端口的信息可区分。 中继部分基于存储在第二存储器中的信息来限制端口，该端口将寻址到不存储在第一存储器中的节点的帧泛洪。

公开(公告)号：US09185076B2

公开(公告)日：2015-11-10

申请号：US12619500

申请日：2009-11-16

申请人： Osamu Shiraki

发明人： Osamu Shiraki

IPC分类号： H04L29/06 ,  H04L12/721

CPC分类号： H04L63/0227 ,  H04L29/06925 ,  H04L45/32 ,  H04L63/1458 ,  H04L69/22 ,  H04L2463/141 ,  H04L2463/142 ,  H04L2463/143 ,  H04L2463/144 ,  H04L2463/145

摘要： A packet processing apparatus includes a static pattern matcher comparing pattern information defining a packet to be filtered with a value regarding at least a part of a received packet, the pattern information being stored by a pattern information manager. A frequency calculator calculates the frequency of matching by the static pattern matcher. A dynamic pattern matcher matches the frequency and a preset comparison value and a processing determiner determines a processing on the received packet based upon the dynamic pattern match.

摘要翻译： 分组处理装置包括：静态模式匹配器，其将定义要过滤的分组的模式信息与关于所接收分组的至少一部分的值进行比较，所述模式信息由模式信息管理器存储。 频率计算器通过静态模式匹配器计算匹配频率。 动态模式匹配器匹配频率和预设比较值，并且处理确定器基于动态模式匹配来确定对接收到的分组的处理。

公开(公告)号：US08774175B2

公开(公告)日：2014-07-08

申请号：US13209634

申请日：2011-08-15

申请人： Osamu Shiraki

发明人： Osamu Shiraki

IPC分类号： H04L12/50 ,  H04L12/28 ,  H04L12/56

CPC分类号： H04L12/2838 ,  H04L12/2809 ,  H04L45/245 ,  H04L2012/2849

摘要： A relay system includes a first relay apparatus connected to a node through a first line and a second relay apparatus connected to the node through a second line. The first line and the second line belong to the same link aggregation group. The first relay apparatus includes a first control unit. The first control unit notifies, before relaying a received frame, the second relay apparatus of a source address included in the received frame in the absence of first relation information related to the source address in the first storage unit upon receiving the received frame via a port connected to the first line. The second relay apparatus includes a second control unit. The second control unit stores, in the second storage unit, second relation information regarding a relationship between the source address notified by the first relay apparatus and an output port connected to the second line.

摘要翻译： 中继系统包括通过第一线路连接到节点的第一中继装置和通过第二线路连接到节点的第二中继装置。 第一行和第二行属于同一链路聚合组。 第一中继装置包括第一控制单元。 第一控制单元在接收到帧之前，在接收帧中包含的源地址的第二中继装置在通过端口接收到接收到的帧时，在没有与第一存储单元中的源地址相关的第一关系信息的情​​况下通知 连接到第一行。 第二中继装置包括第二控制单元。 第二控制单元在第二存储单元中存储关于由第一中继设备通知的源地址与连接到第二线路的输出端口之间的关系的第二关系信息。

公开(公告)号：US07760763B2

公开(公告)日：2010-07-20

申请号：US12339472

申请日：2008-12-19

申请人： Osamu Shiraki

发明人： Osamu Shiraki

IPC分类号： H04J3/26

CPC分类号： H04L63/0227

摘要： A packet transfer controlling apparatus includes a depth storage unit that stores a pattern and a depth in association with each other. When accepting a setting of the pattern, the apparatus searches the depth storage unit by using the accepted pattern to obtain the depth stored in association with the pattern, thereby deriving the depth of the information to be extracted from the input packet. Upon accepting the input of the packet, information is extracted sequentially from the head of the packet. The apparatus determines whether the extracted information is positioned at a location deeper than the derived depth. When determining that the extracted information is not yet positioned at a location deeper than the derived depth, the apparatus continues extraction of information. When determining that the extracted information is positioned at a location deeper than the depth, the apparatus ends extraction of information.

摘要翻译： 分组传送控制装置包括深度存储单元，其相互关联地存储图案和深度。 当接收到图案的设置时，装置通过使用接受的图案来搜索深度存储单元，以获得与图案相关联存储的深度，从而从输入分组导出要提取的信息的深度。 在接收到分组的输入后，从分组的头部顺序地提取信息。 该装置确定所提取的信息是否位于比导出的深度更深的位置。 当确定提取的信息尚未位于比导出深度更深的位置时，设备继续提取信息。 当确定提取的信息位于比深度更深的位置时，设备结束信息的提取。