公开(公告)号：US20030087517A1

公开(公告)日：2003-05-08

申请号：US09993749

申请日：2001-11-06

Applicant: ProMOS Technologies, Inc.

Inventor： Brian Lee

IPC: H01L021/4763

CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L27/10829 ,  H01L27/10888

Abstract: A consolidated junction contact etch in the fabrication of a DRAM integrated circuit device is described. Semiconductor device structures are provided in and on a substrate wherein the substrate is divided into an active area and a periphery area. The semiconductor device structures are covered with an etch stop layer. A dielectric layer is deposited over the etch stop layer. The dielectric layer is concurrently etched through in the active area to form bit line contact openings, in the periphery area to form substrate contact openings, and to form gate contact openings wherein the etching stops at the etch stop layer. The etch stop layer is etched into to a lesser extent through the substrate contact openings and the bit line contact openings than through the gate contact openings. Then, the etch stop layer is etched through using a directional etch selective to the etch stop layer. The bit line contact openings, substrate contact openings, and gate contact openings are filled with a conducting layer to complete formation of contacts in the fabrication of a DRAM integrated circuit device.

Abstract translation: 描述了在DRAM集成电路器件的制造中的固结结接点蚀刻。 半导体器件结构设置在衬底中和衬底上，其中衬底被分为有源区域和外围区域。 半导体器件结构被蚀刻停止层覆盖。 介电层沉积在蚀刻停止层上。 介电层同时蚀刻穿过有源区域，以形成位线接触开口，在周边区域形成衬底接触开口，并形成栅极接触开口，其中蚀刻在蚀刻停止层处停止。 蚀刻停止层通过基板接触开口和位线接触开口被蚀刻到较小程度，而不是通过栅极接触开口。 然后，通过使用对蚀刻停止层选择性的定向蚀刻蚀刻蚀刻停止层。 位线接触开口，基板接触开口和栅极接触开口填充有导电层，以在DRAM集成电路器件的制造中完成触点的形成。

公开(公告)号：US20030087492A1

公开(公告)日：2003-05-08

申请号：US10000922

申请日：2001-11-02

Applicant: PROMOS TECHNOLOGIES, INC.

Inventor： Brian Lee ,  Jan G. Zieleman

IPC: H01L021/8234 ,  H01L021/8244 ,  H01L021/8242 ,  H01L021/20

CPC classification number: H01L27/1087 ,  C07K14/43504 ,  C07K14/43595 ,  C07K2319/60 ,  H01L21/3144 ,  H01L21/31604 ,  H01L29/66181

Abstract: The present invention discloses structure and manufacturing method of binary nitride-oxide (NO) dielectric node for deep trench based DRAM devices. In the present invention, a thin strained SiGe layer is deposited prior to poly deposition to modulate the chemical potential unbalance caused by work-function (WF) differences between buried plate and poly. The thin strained SiGe layer will lower the differences by its lower band-gap characteristics at the same doping level, thereby balancing the chemical potential despite of a different doping. The modulation of the chemical potential can be achieved by a proper control of a stochimetric x value. The optimized chemical potential will assure the reliability and robustness of the dielectric node, especially the binary NO dielectric node by suppressing asymmetric charging trapping and charge injection nature.

Abstract translation: 本发明公开了用于深沟槽DRAM器件的二元氮化物（NO）介质节点的结构和制造方法。 在本发明中，在多晶沉积之前沉积薄的应变SiGe层，以调制由掩埋板和多晶硅之间的功函数（WF）差引起的化学势不平衡。 薄应变SiGe层将通过其相同掺杂水平下的较低带隙特性降低差异，从而尽管掺杂不同，仍能平衡化学势。 化学势的调制可以通过适当控制随机值x来实现。 优化的化学势将通过抑制非对称充电捕获和电荷注入性质来确保介质节点，特别是二元NO介质节点的可靠性和鲁棒性。

公开(公告)号：US20030109140A1

公开(公告)日：2003-06-12

申请号：US10020754

申请日：2001-12-12

Applicant: ProMOS Technologies, Inc.

Inventor： Brian Lee

IPC: H01L021/302 ,  H01L021/461 ,  H01L021/311

CPC classification number: H01L27/10867 ,  H01L21/76224

Abstract: An improved buried strap method in the fabrication of a DRAM integrated circuit device is described. A deep trench is etched into a substrate. A collar is formed on an upper portion of the deep trench. A buried plate is formed by doping around a lower portion of the deep trench and a capacitor dielectric layer is formed within the deep trench. The deep trench is filled with a silicon layer wherein the silicon layer forms a deep trench capacitor and covers the collar. The silicon layer is recessed below a top surface of the substrate to leave a recess. A top portion of the collar is etched away to leave a collar divot. A hemispherical grain polysilicon layer is selectively deposited into the deep trench and filling the collar divot. The HSG layer is doped in-situ or by post plasma doping. The doped hemispherical grain polysilicon layer forms a buried strap in the fabrication of a deep trench DRAM integrated circuit device.

Abstract translation: 描述了在DRAM集成电路器件的制造中改进的掩埋带方法。 将深沟槽刻蚀成衬底。 在深沟槽的上部形成套环。 通过掺杂在深沟槽的下部周围形成掩埋板，并且在深沟槽内形成电容器电介质层。 深沟槽填充有硅层，其中硅层形成深沟槽电容器并覆盖套环。 硅层在衬底的顶表面下方凹入以留下凹槽。 将衣领的顶部蚀刻掉以留下衣领。 半球形晶粒多晶硅层被选择性地沉积到深沟槽中并填充套环。 HSG层原位掺杂或通过后等离子体掺杂。 掺杂的半球晶粒多晶硅层在深​​沟槽DRAM集成电路器件的制造中形成掩埋带。