公开(公告)号：US06927432B2

公开(公告)日：2005-08-09

申请号：US10640856

申请日：2003-08-13

申请人： Paige M. Holm ,  Jon J. Candelaria

发明人： Paige M. Holm ,  Jon J. Candelaria

IPC分类号： H01L27/146 ,  H01L31/062 ,  H01L31/62

CPC分类号： H01L27/14643 ,  H01L27/1463 ,  H01L27/14636

摘要： An exemplary system and method for providing a vertically integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS layer (420); and a photosensing element (380) fabricated in a vertically integrated optically active layer (320, 350), where the optically active layer (320, 350) is bonded to the CMOS layer (420) and the optically active layer (320, 350) is positioned near a metalization surface (405) of the CMOS layer (420). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics. Exemplary embodiments of the present invention representatively provide for integrated photosensing components that may be readily incorporated with existing technologies for the improvement of CMOS imaging, device package form factors, weights and/or other manufacturing, device or material performance metrics.

摘要翻译： 公开了一种用于提供适合于在CMOS成像应用中使用的垂直集成光敏元件的示例性系统和方法，其特别包括：经处理的CMOS层（420）; 以及在垂直集成的光学有源层（320,350）中制造的光敏元件（380），其中光学活性层（320,350）被结合到CMOS层（420）和光学活性层（320,350） 位于CMOS层（420）的金属化表面（405）附近。 公开的特征和规格可以被不同地控制，配置，适配或以其他方式任意地修改，以进一步改善或以其它方式优化光敏性能或其它材料特性。 本发明的示例性实施例代表性地提供了可以容易地与现有技术结合以用于改进CMOS成像，设备封装外形，重量和/或其它制造，器件或材料性能度量的集成光敏元件。

公开(公告)号：US06809008B1

公开(公告)日：2004-10-26

申请号：US10652632

申请日：2003-08-28

申请人： Paige M. Holm ,  Jon J. Candelaria

发明人： Paige M. Holm ,  Jon J. Candelaria

IPC分类号： H01L2130

CPC分类号： H01L27/14634 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/1464 ,  H01L27/1469 ,  H01L2924/0002 ,  H01L2924/00

摘要： An exemplary system and method for providing an integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS host wafer (460) bonded with a monocrystalline, optically active donor wafer (300); a photosensing element (390) integrated in said optically active donor wafer (300) having an interconnect via (505, 495, 485) substantially decoupled from the photosensing element (390), wherein the host (460) and donor (300) wafers are bonded through the optically active material in a region disposed near a metalization surface (450, 455, 445) of the CMOS layer (460) in order to allow fabrication of the interconnect (505, 495, 485). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics. Exemplary embodiments of the present invention representatively provide for integrated photosensing components that may be readily incorporated with existing technologies for the improvement of CMOS imaging, device package form factors, weights and/or other manufacturing, device or material performance metrics.

摘要翻译： 公开了一种用于提供适合于在CMOS成像应用中使用的集成光敏元件的示例性系统和方法，其特别包括：与单晶光学活性施主晶片（300）接合的经处理的CMOS主晶片（460）; 集成在所述光学活性施主晶片（300）中的光敏元件（390）具有与光敏元件（390）基本上分离的互连通孔（505,495,485），其中主体（460）和供体（300）晶片是 通过光学活性材料在设置在CMOS层（460）的金属化表面（450,455,445）附近的区域中，以便制造互连（505,495,485）。 公开的特征和规格可以被不同地控制，配置，适配或以其他方式任意地修改，以进一步改善或以其它方式优化光敏性能或其它材料特性。 本发明的示例性实施例代表性地提供了可以容易地与现有技术结合以用于改进CMOS成像，设备封装外形，重量和/或其它制造，器件或材料性能度量的集成光敏元件。

公开(公告)号：US06984816B2

公开(公告)日：2006-01-10

申请号：US10641216

申请日：2003-08-13

申请人： Paige M. Holm ,  Jon J. Candelaria

发明人： Paige M. Holm ,  Jon J. Candelaria

IPC分类号： H01J40/14

CPC分类号： H01L27/14601 ,  H01L27/14636 ,  H01L27/14643

摘要： An exemplary system and method for providing a vertically integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS layer (420); and a photosensing element (380) fabricated in a vertically integrated optically active layer (320, 350), where the optically active layer (320, 350) is bonded to the CMOS layer (420) and the optically active layer (320, 350) is positioned near a metalization surface (405) of the CMOS layer (420). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics. Exemplary embodiments of the present invention representatively provide for integrated photosensing components that may be readily incorporated with existing technologies for the improvement of CMOS imaging, device package form factors, weights and/or other manufacturing, device or material performance metrics.

摘要翻译： 公开了一种用于提供适合于在CMOS成像应用中使用的垂直集成光敏元件的示例性系统和方法，其特别包括：经处理的CMOS层（420）; 以及在垂直集成的光学有源层（320,350）中制造的光敏元件（380），其中光学活性层（320,350）被结合到CMOS层（420）和光学活性层（320,350） 位于CMOS层（420）的金属化表面（405）附近。 公开的特征和规格可以被不同地控制，配置，适配或以其他方式任意地修改，以进一步改善或以其它方式优化光敏性能或其它材料特性。 本发明的示例性实施例代表性地提供了可以容易地与现有技术结合以用于改进CMOS成像，设备封装外形，重量和/或其它制造，器件或材料性能度量的集成光敏元件。

公开(公告)号：US09720051B2

公开(公告)日：2017-08-01

申请号：US14290040

申请日：2014-05-29

申请人： Paige M. Holm ,  Lianjun Liu

发明人： Paige M. Holm ,  Lianjun Liu

IPC分类号： G01R33/09 ,  G01R33/00 ,  G01R35/00

CPC分类号： G01R33/0023 ,  G01R33/09 ,  G01R35/005

摘要： A magnetic field sensor includes in-plane sense elements located in a plane of the magnetic field sensor and configured to detect a magnetic field oriented perpendicular to the plane. A current carrying structure is positioned proximate the magnetic field sensor and includes at least one coil surrounding the in-plane sense elements. An electric current is applied to the coil to create a self-test magnetic field to be sensed by the sense elements. The coil may be vertically displaced from the plane in which the sense elements are located and laterally displaced from an area occupied by the sense elements to produce both Z-axis magnetic field components and lateral magnetic field components of the self-test magnetic field. The sense elements are arranged within the coil and interconnected to cancel the lateral magnetic field components, while retaining the Z-axis magnetic field components to be used for self-test of the magnetic field sensor.

公开(公告)号：US08659167B1

公开(公告)日：2014-02-25

申请号：US13597824

申请日：2012-08-29

申请人： Philip H. Bowles ,  Paige M. Holm ,  Stephen R. Hooper ,  Raymond M. Roop

发明人： Philip H. Bowles ,  Paige M. Holm ,  Stephen R. Hooper ,  Raymond M. Roop

IPC分类号： H01L29/84

CPC分类号： H01L23/528 ,  B81C1/0023 ,  B81C1/00238 ,  B81C2201/019 ,  B81C2203/0792 ,  H01L2224/48091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method (80) entails providing (82) a structure (117), providing (100) a controller element (102, 24), and bonding (116) the controller element to an outer surface (52, 64) of the structure. The structure includes a sensor wafer (92) and a cap wafer (94). Inner surfaces (34, 36) of the wafers (92, 94) are coupled together, with sensors (30) interposed between the wafers. One wafer (94, 92) includes a substrate portion (40, 76) with bond pads (42) formed on its inner surface (34, 36). The other wafer (94, 92) conceals the substrate portion (40, 76). After bonding, methodology (80) entails forming (120) conductive elements (60) on the element (102, 24), removing (126) material sections (96, 98, 107) from the wafers to expose the bond pads, forming (130) electrical interconnects (56), applying (134) packaging material (64), and singulating (138) to produce sensor packages (20, 70).

摘要翻译： 方法（80）需要提供（82）结构（117），提供（100）控制器元件（102,24），并将控制器元件（116）结合（116）到结构的外表面（52,64）。 该结构包括传感器晶片（92）和盖晶片（94）。 晶片（92,94）的内表面（34,36）被耦合在一起，传感器（30）置于晶片之间。 一个晶片（94,92）包括具有形成在其内表面（34,36）上的接合焊盘（42）的衬底部分（40,76）。 另一个晶片（94,92）隐藏基板部分（40,76）。 在结合之后，方法学（80）需要在元件（102,24）上形成（120）导电元件（60），从晶片去除（126）材料部分（96,98,107）以暴露接合焊盘，形成 130）电互连（56），施加（134）包装材料（64）和单分离（138）以产生传感器封装（20,70）。

公开(公告)号：US20130335065A1

公开(公告)日：2013-12-19

申请号：US13523675

申请日：2012-06-14

申请人： Kevin R. Fugate ,  Edward W. Carstens ,  Paige M. Holm ,  Dean W. Miller

发明人： Kevin R. Fugate ,  Edward W. Carstens ,  Paige M. Holm ,  Dean W. Miller

IPC分类号： G01R33/00 ,  G01R35/00

CPC分类号： G01R33/0035 ,  G01R33/0047 ,  G01R33/0082 ,  G01R33/098

摘要： Apparatus, systems, and methods are provided for sensing devices. An exemplary sensing device includes a sensing arrangement on a substrate to sense a first property, a heating arrangement, and a control system coupled to the first sensing arrangement and the heating arrangement to activate the heating arrangement to heat the first sensing arrangement and deactivate the heating arrangement while obtaining one or more measurement values for the first property from the first sensing arrangement.

摘要翻译： 提供了用于感测装置的装置，系统和方法。 一种示例性感测装置包括：感测装置，用于感测第一属性的基板上的感测装置，加热装置和耦合到第一感测装置和加热装置的控制系统，以激活加热装置以加热第一感测装置并使加热失效 同时从第一感测装置获得用于第一属性的一个或多个测量值。

公开(公告)号：US20080285813A1

公开(公告)日：2008-11-20

申请号：US11747985

申请日：2007-05-14

申请人： Paige M. Holm

发明人： Paige M. Holm

IPC分类号： G06K9/00

CPC分类号： G06K9/00013 ,  G06K9/00885

摘要： An apparatus and method is provided for recognizing ear biometrics of an approved user of a wireless device. The apparatus comprises a wireless communication device (50) including a first biometric device (52) for assessing the identity of the user, the biometric device (52) comprising a touch input display (52) including a plurality of pixels for providing a visual output, and a plurality of sensors (84), one each being incorporated within one of the plurality of pixels (82), for recording at least a partial image of a user's ear (10) when the touch input display (52) is placed against an ear (10) of the user in a first mode and for receiving an input in response to being touched by the user in a second mode. A controller (120) is coupled to the first biometric device (52) in the first mode, wherein the controller (120) enables the function when the identity of the user is verified by the first biometric device (52). Additional biometric devices may be included wherein a positive response from one of the biometric devices enables the function of the wireless device.

摘要翻译： 提供了一种用于识别无线设备的认可用户的耳朵生物特征的装置和方法。 该装置包括无线通信设备（50），该无线通信设备包括用于评估用户身份的第一生物测定设备（52），所述生物测定设备（52）包括触摸输入显示器（52），所述触摸输入显示器包括用于提供视觉输出的多个像素 ，以及多个传感器（84），每个传感器（84）被并入在所述多个像素（82）中的一个内，用于当所述触摸输入显示器（52）被放置在所述多个像素（82）中时，用于记录用户耳朵（10）的至少部分图像 用户的耳朵（10）处于第一模式，并且响应于在第二模式中被用户触摸而接收输入。 控制器（120）在第一模式下耦合到第一生物测定装置（52），其中当用户的身份被第一生物测定装置（52）验证时，控制器（120）启用该功能。 可以包括附加的生物测定装置，其中来自生物测定装置之一的肯定响应使得无线装置的功能成为可能。

公开(公告)号：US06965128B2

公开(公告)日：2005-11-15

申请号：US10356549

申请日：2003-02-03

申请人： Paige M. Holm ,  Barbara Foley Barenburg ,  Joyce K. Yamamoto ,  Fred V. Richard

发明人： Paige M. Holm ,  Barbara Foley Barenburg ,  Joyce K. Yamamoto ,  Fred V. Richard

IPC分类号： H01L21/8258 ,  H01L27/01 ,  H01L27/06 ,  H01L33/00

CPC分类号： H01L27/0605 ,  H01L21/8258

摘要： High quality epitaxial layers of monocrystalline materials (26) can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy and epitaxial growth of single crystal silicon onto single crystal oxide materials. A microresonator device is formed overlying the monocrystalline substrate. Portions or an entirety of the microresonator device can also overly the accommodating buffer layer, or the monocrystalline material layer.

摘要翻译： 通过形成用于生长单晶层的顺应性衬底，可以将单晶材料（26）的高质量外延层生长成覆盖在单晶衬底（22）如大硅晶片上。 容纳缓冲层（24）包括通过氧化硅的非晶界面层（28）与硅晶片隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的单晶硅在单晶氧化物材料上的外延和外延生长。 在单晶衬底上形成微谐振器器件。 部分或整个微谐振器装置也可以过度地容纳缓冲层或单晶材料层。

公开(公告)号：US5893721A

公开(公告)日：1999-04-13

申请号：US823382

申请日：1997-03-24

申请人： Rong-Ting Huang ,  Phil Wright ,  Paige M. Holm

发明人： Rong-Ting Huang ,  Phil Wright ,  Paige M. Holm

IPC分类号： H01L27/15 ,  H01L27/32 ,  H01L33/00

CPC分类号： H01L27/3276 ,  H01L27/156

摘要： A method of fabricating an active matrix LED array includes forming layers of material on a substrate, which layers cooperate to emit light when activated. Row and column dividers are formed in the layers to divide the layers into an array of LEDs arranged in rows and columns. One FET is formed on the row dividers in association with each LED and a source of each FET is connected to an anode of the associated LED. Row and column buses are formed on the row and column dividers, respectively, and the drain of each FET is connected to an adjacent row bus with the gate of each FET being connected to an adjacent column bus. A cathode for each LED is connected as a common terminal for all of the LEDs in the array.

摘要翻译： 制造有源矩阵LED阵列的方法包括在衬底上形成材料层，这些层在激活时协同发光。 行和列分隔器形成在层中以将层划分成以行和列布置的LED阵列。 一个FET与每个LED相关联地在行分隔器上形成，并且每个FET的源极连接到相关联的LED的阳极。 行和列总线分别形成在行和列分频器上，并且每个FET的漏极连接到相邻的行总线，每个FET的栅极连接到相邻的列总线。 每个LED的阴极作为阵列中的所有LED的公共端子连接。

公开(公告)号：US5866922A

公开(公告)日：1999-02-02

申请号：US772448

申请日：1996-12-23

申请人： Rong Ting Huang ,  Phil Wright ,  Paige M. Holm ,  Song Q. Shi

发明人： Rong Ting Huang ,  Phil Wright ,  Paige M. Holm ,  Song Q. Shi

IPC分类号： H01L27/32 ,  H01L33/00 ,  H05B33/00 ,  H05B33/06

CPC分类号： H01L27/3225 ,  H01L27/3211

摘要： An integrated matrix of light emitting devices includes a plurality of isolated semiconductor LEDs positioned in a matrix of rows and columns on the surface of a substrate. A plurality of column buses, one each positioned adjacent each column of semiconductor LEDs, is provided with each of the column buses being connected to a first terminal of each semiconductor LED in the adjacent column of semiconductor LEDs and each of the column buses providing an exposed planar surface. A plurality of OEDs is positioned on the exposed planar surface of each column bus with a first terminal of each OED connected to the column bus.

摘要翻译： 发光器件的集成矩阵包括位于衬底表面上的行和列的矩阵中的多个隔离半导体LED。 多个列式总线（每个定位在每列半导体LED的每一列中）设置有每个列总线连接到相邻的半导体LED列中的每个半导体LED的第一端子，并且每个列总线提供暴露的 平面。 多个OED被定位在每个列总线的暴露的平面上，每个OED的第一端连接到列总线。