公开(公告)号：US5925143A

公开(公告)日：1999-07-20

申请号：US857974

申请日：1997-05-16

申请人： Pamela Sue Gillis ,  Ravi Kumar Kolagotla ,  Dennis A. Miller ,  Maria Noack ,  Steven Frederick Oakland ,  Chris Joseph Rebeor ,  Thomas Gregory Sopchak ,  Jeanne Trinko-Mechler

发明人： Pamela Sue Gillis ,  Ravi Kumar Kolagotla ,  Dennis A. Miller ,  Maria Noack ,  Steven Frederick Oakland ,  Chris Joseph Rebeor ,  Thomas Gregory Sopchak ,  Jeanne Trinko-Mechler

IPC分类号： G01R31/3185 ,  G11C29/32 ,  G01R31/28

CPC分类号： G01R31/318586 ,  G01R31/318558 ,  G11C29/32

摘要： A scan architecture for testing integrated circuit chips containing scannable memory devices, such as register arrays, is operable in a bypass mode during which only a small portion of the memory cells in each device or array is inserted in the scan path to substantially reduce scan path length, test time and test data volume during testing of other logic components in the circuit chip. Additional decoder logic is employed to select a small number of words in the device or array during the scan-bypass mode, and multiplexor circuitry removes the bypassed words from the scan path. By leaving the small number of the register array words in the scan path, observability of logic upstream of the array, and controllability of logic downstream of the array, is preserved during the bypass mode without the need for additional shift register latches and other external logic components.

摘要翻译： 用于测试包含可扫描存储器设备（诸如寄存器阵列）的集成电路芯片的扫描架构可在旁路模式中操作，在该旁路模式期间，每个器件或阵列中只有一小部分存储器单元插入到扫描路径中以基本上减少扫描路径 电路芯片中其他逻辑元件测试期间的长度，测试时间和测试数据量。 采用附加解码器逻辑在扫描旁路模式期间在器件或阵列中选择少量字，并且多路复用器电路从扫描路径中去除旁路字。 通过将少量的寄存器阵列字留在扫描路径中，在旁路模式期间保留阵列上游逻辑的可观察性和阵列下游逻辑的可控性，而不需要额外的移位寄存器锁存器和其他外部逻辑 组件。

公开(公告)号：US5719879A

公开(公告)日：1998-02-17

申请号：US577676

申请日：1995-12-21

申请人： Pamela Sue Gillis ,  Ravi Kumar Kolagotla ,  Dennis A. Miller ,  Maria Noack ,  Steven Frederick Oakland ,  Chris Joseph Rebeor ,  Thomas Gregory Sopchak ,  Jeanne Trinko-Mechler

发明人： Pamela Sue Gillis ,  Ravi Kumar Kolagotla ,  Dennis A. Miller ,  Maria Noack ,  Steven Frederick Oakland ,  Chris Joseph Rebeor ,  Thomas Gregory Sopchak ,  Jeanne Trinko-Mechler

IPC分类号： G01R31/3185 ,  G11C29/32 ,  G01R31/28

CPC分类号： G01R31/318586 ,  G01R31/318558 ,  G11C29/32

摘要： A scan architecture for testing integrated circuit chips containing scannable memory devices, such as register arrays, is operable in a bypass mode during which only a small portion of the memory cells in each device or array is inserted in the scan path to substantially reduce scan path length, test time and test data volume during testing of other logic components in the circuit chip. Additional decoder logic is employed to select a small number of words in the device or array during the scan-bypass mode, and multiplexor circuitry removes the bypassed words from the scan path. By leaving the small number of the register array words in the scan path, observability of logic upstream of the array, and controllability of logic downstream of the array, is preserved during the bypass mode without the need for additional shift register latches and other external logic components.