公开(公告)号：US20070129920A1

公开(公告)日：2007-06-07

申请号：US11275035

申请日：2005-12-05

申请人： Francis Kampf ,  Jeanne Trinko-Mechler ,  David Stauffer

发明人： Francis Kampf ,  Jeanne Trinko-Mechler ,  David Stauffer

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G01R31/318314

摘要： Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

摘要翻译： 本文的实施例提供了一种用于串行器/解串器数据路径系统的自动化仿真测试台生成的方法。 该方法提供用于生成和检查数据路径系统内的数据的事务处理器的数据库，其中事务处理器适用于数据通路系统的任意配置。 数据库提供了每个核心单个事务处理器集合。 接下来，该方法自动从数据库中选择一组事务处理器，以便包含在仿真测试台中。 接下来，该方法通过将所选择的一组事务处理器与数据路径系统相互连接，通过数据路径系统映射第一个数据路径和第二个数据路径。 该方法还包括设置核上的控制引脚以便于数据通过数据路径系统的核心的传播。 随后，控制引脚被跟踪到输入端口和控制寄存器。

公开(公告)号：US08135558B2

公开(公告)日：2012-03-13

申请号：US12169668

申请日：2008-07-09

申请人： Francis A. Kampf ,  Jeanne Trinko-Mechler ,  David R. Stauffer

发明人： Francis A. Kampf ,  Jeanne Trinko-Mechler ,  David R. Stauffer

IPC分类号： G06F11/00 ,  G06F19/00

CPC分类号： G06F17/5022 ,  G01R31/318314

摘要： Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

摘要翻译： 本文的实施例提供了一种用于串行器/解串器数据路径系统的自动化仿真测试台生成的方法。 该方法提供用于生成和检查数据路径系统内的数据的事务处理器的数据库，其中事务处理器适用于数据通路系统的任意配置。 数据库提供了每个核心单个事务处理器集合。 接下来，该方法自动从数据库中选择一组事务处理器，以便包含在仿真测试台中。 接下来，该方法通过将所选择的一组事务处理器与数据路径系统相互连接，通过数据路径系统映射第一个数据路径和第二个数据路径。 该方法还包括设置核上的控制引脚以便于数据通过数据路径系统的核心的传播。 随后，控制引脚被跟踪到输入端口和控制寄存器。

公开(公告)号：US5925143A

公开(公告)日：1999-07-20

申请号：US857974

申请日：1997-05-16

申请人： Pamela Sue Gillis ,  Ravi Kumar Kolagotla ,  Dennis A. Miller ,  Maria Noack ,  Steven Frederick Oakland ,  Chris Joseph Rebeor ,  Thomas Gregory Sopchak ,  Jeanne Trinko-Mechler

发明人： Pamela Sue Gillis ,  Ravi Kumar Kolagotla ,  Dennis A. Miller ,  Maria Noack ,  Steven Frederick Oakland ,  Chris Joseph Rebeor ,  Thomas Gregory Sopchak ,  Jeanne Trinko-Mechler

IPC分类号： G01R31/3185 ,  G11C29/32 ,  G01R31/28

CPC分类号： G01R31/318586 ,  G01R31/318558 ,  G11C29/32

摘要： A scan architecture for testing integrated circuit chips containing scannable memory devices, such as register arrays, is operable in a bypass mode during which only a small portion of the memory cells in each device or array is inserted in the scan path to substantially reduce scan path length, test time and test data volume during testing of other logic components in the circuit chip. Additional decoder logic is employed to select a small number of words in the device or array during the scan-bypass mode, and multiplexor circuitry removes the bypassed words from the scan path. By leaving the small number of the register array words in the scan path, observability of logic upstream of the array, and controllability of logic downstream of the array, is preserved during the bypass mode without the need for additional shift register latches and other external logic components.

摘要翻译： 用于测试包含可扫描存储器设备（诸如寄存器阵列）的集成电路芯片的扫描架构可在旁路模式中操作，在该旁路模式期间，每个器件或阵列中只有一小部分存储器单元插入到扫描路径中以基本上减少扫描路径 电路芯片中其他逻辑元件测试期间的长度，测试时间和测试数据量。 采用附加解码器逻辑在扫描旁路模式期间在器件或阵列中选择少量字，并且多路复用器电路从扫描路径中去除旁路字。 通过将少量的寄存器阵列字留在扫描路径中，在旁路模式期间保留阵列上游逻辑的可观察性和阵列下游逻辑的可控性，而不需要额外的移位寄存器锁存器和其他外部逻辑 组件。

公开(公告)号：US20080270065A1

公开(公告)日：2008-10-30

申请号：US12169668

申请日：2008-07-09

申请人： Francis A. Kampf ,  Jeanne Trinko-Mechler ,  David R. Stauffer

发明人： Francis A. Kampf ,  Jeanne Trinko-Mechler ,  David R. Stauffer

IPC分类号： H01Q19/00

CPC分类号： G06F17/5022 ,  G01R31/318314

摘要： Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

摘要翻译： 本文的实施例提供了一种用于串行器/解串器数据路径系统的自动化仿真测试台生成的方法。 该方法提供用于生成和检查数据路径系统内的数据的事务处理器的数据库，其中事务处理器适用于数据通路系统的任意配置。 数据库提供了每个核心单个事务处理器集合。 接下来，该方法自动从数据库中选择一组事务处理器，以便包含在仿真测试台中。 接下来，该方法通过将所选择的一组事务处理器与数据路径系统相互连接，通过数据路径系统映射第一个数据路径和第二个数据路径。 该方法还包括设置核上的控制引脚以便于数据通过数据路径系统的核心的传播。 随后，控制引脚被跟踪到输入端口和控制寄存器。

公开(公告)号：US20050257179A1

公开(公告)日：2005-11-17

申请号：US10709528

申请日：2004-05-12

申请人： David Stauffer ,  Jeanne Trinko-Mechler

发明人： David Stauffer ,  Jeanne Trinko-Mechler

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A method, system and program product for building an automated bit-sliced datapath system generating tool so design can be performed at a higher level, and automated generation of the synthesizable HDL representation can be accomplished are disclosed. A method defines datapath system characteristics, defines core/pin rules, and then constructs class-type inference rules that can be used for automatically generating the datapath system. An “orthogonal bundling” technique is used that groups pin by a class, and also by a channel identifier. The class-type inference rule corresponding to each class uses of the following factors to infer appropriate wiring: 1) number and type of pins in the class created by the instantiation of cores by the user; 2) attribute definitions on pins set by library core/pin rules; 3) user selection of “global attributes”; 4) user definition of channel bit order (“link orders”) to imply the order of connection between stages; and 5) user-defined attributes set on pin classes.

摘要翻译： 可以在更高层次上执行用于构建自动位片数据路径系统生成工具的设计的方法，系统和程序产品，并且可以实现自动生成可综合的HDL表示。 一种方法定义数据路径系统特性，定义核心/引脚规则，然后构建可用于自动生成数据路径系统的类类型推理规则。 使用“正交捆绑”技术，其通过类分组引脚，并且还使用通道标识符。 对应于每个类的类型推理规则使用以下因素来推断适当的布线：1）由用户实例化核心创建的类中的引脚数量和类型; 2）由库核心/引脚规则设置的引脚上的属性定义; 3）用户选择“全局属性”; 4）用户定义通道位顺序（“链接顺序”）以表示阶段之间的连接顺序; 和5）用户定义的属性设置在引脚类上。

公开(公告)号：US07444258B2

公开(公告)日：2008-10-28

申请号：US11275035

申请日：2005-12-05

申请人： Francis A. Kampf ,  Jeanne Trinko-Mechler ,  David R. Stauffer

发明人： Francis A. Kampf ,  Jeanne Trinko-Mechler ,  David R. Stauffer

IPC分类号： G01R31/00 ,  G06F19/00

CPC分类号： G06F17/5022 ,  G01R31/318314

摘要： Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

摘要翻译： 本文的实施例提供了一种用于串行器/解串器数据路径系统的自动化仿真测试台生成的方法。 该方法提供用于生成和检查数据路径系统内的数据的事务处理器的数据库，其中事务处理器适用于数据通路系统的任意配置。 数据库提供了每个核心单个事务处理器集合。 接下来，该方法自动从数据库中选择一组事务处理器，以便包含在仿真测试台中。 接下来，该方法通过将所选择的一组事务处理器与数据路径系统相互连接，通过数据路径系统映射第一个数据路径和第二个数据路径。 该方法还包括设置核上的控制引脚以便于数据通过数据路径系统的核心的传播。 随后，控制引脚被跟踪到输入端口和控制寄存器。

公开(公告)号：US07290238B2

公开(公告)日：2007-10-30

申请号：US10709528

申请日：2004-05-12

申请人： David R. Stauffer ,  Jeanne Trinko-Mechler

发明人： David R. Stauffer ,  Jeanne Trinko-Mechler

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： An automated bit-sliced datapath system generating tool is built so design can be performed at a higher level, and automated generation of the synthesizable HDL representation can be accomplished are disclosed. A method defines datapath system characteristics, defines core/pin rules, and then constructs class-type inference rules that can be used for automatically generating the datapath system. An “orthogonal bundling” technique is used that groups pin by a class, and also by a channel identifier. The class-type inference rule corresponding to each class uses of the following factors to infer appropriate wiring: 1) number and type of pins in the class created by the instantiation of cores by the user; 2) attribute definitions on pins set by library core/pin rules; 3) user selection of “global attributes”; 4) user definition of channel bit order (“link orders”) to imply the order of connection between stages; and 5) user-defined attributes set on pin classes.

摘要翻译： 构建了一种自动的位片式数据路径系统生成工具，从而可以在更高级别进行设计，并且可以实现自动生成可综合的HDL表示。 一种方法定义数据路径系统特性，定义核心/引脚规则，然后构建可用于自动生成数据路径系统的类类型推理规则。 使用“正交捆绑”技术，其通过类分组引脚，并且还使用通道标识符。 对应于每个类的类型推理规则使用以下因素来推断适当的布线：1）由用户实例化核心创建的类中的引脚数量和类型; 2）由库核心/引脚规则设置的引脚上的属性定义; 3）用户选择“全局属性”; 4）用户定义通道位顺序（“链接顺序”）以表示阶段之间的连接顺序; 和5）用户定义的属性设置在引脚类上。

公开(公告)号：US5719879A

公开(公告)日：1998-02-17

申请号：US577676

申请日：1995-12-21

申请人： Pamela Sue Gillis ,  Ravi Kumar Kolagotla ,  Dennis A. Miller ,  Maria Noack ,  Steven Frederick Oakland ,  Chris Joseph Rebeor ,  Thomas Gregory Sopchak ,  Jeanne Trinko-Mechler

发明人： Pamela Sue Gillis ,  Ravi Kumar Kolagotla ,  Dennis A. Miller ,  Maria Noack ,  Steven Frederick Oakland ,  Chris Joseph Rebeor ,  Thomas Gregory Sopchak ,  Jeanne Trinko-Mechler

IPC分类号： G01R31/3185 ,  G11C29/32 ,  G01R31/28

CPC分类号： G01R31/318586 ,  G01R31/318558 ,  G11C29/32

摘要： A scan architecture for testing integrated circuit chips containing scannable memory devices, such as register arrays, is operable in a bypass mode during which only a small portion of the memory cells in each device or array is inserted in the scan path to substantially reduce scan path length, test time and test data volume during testing of other logic components in the circuit chip. Additional decoder logic is employed to select a small number of words in the device or array during the scan-bypass mode, and multiplexor circuitry removes the bypassed words from the scan path. By leaving the small number of the register array words in the scan path, observability of logic upstream of the array, and controllability of logic downstream of the array, is preserved during the bypass mode without the need for additional shift register latches and other external logic components.