公开(公告)号：US20160071971A1

公开(公告)日：2016-03-10

申请号：US14820555

申请日：2015-08-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： CHIAKI KUDOU ,  HARUYUKI SORADA ,  TSUNEICHIRO SANO

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/535 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/02131 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/32134 ,  H01L21/32137 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: semiconductor layer having an impurity region of a first conductivity type; a gate insulating layer, at least a part of the gate insulating layer positioned on the semiconductor layer; a gate electrode positioned on the gate insulating layer and having a first surface in contact with the part of the gate insulating film and a second surface opposite to the first surface; an interlayer insulating layer covering the gate electrode; and an electrode in contact with the impurity region. The gate electrode has a recess at a corner in contact with the second surface, in a cross section of the gate electrode perpendicular to a surface of the semiconductor layer. A cavity surrounded by the gate electrode and the interlayer insulating layer is positioned in a region including at least a part of the recess.

Abstract translation: 半导体器件包括：具有第一导电类型的杂质区的半导体层; 栅极绝缘层，栅绝缘层的至少一部分位于半导体层上; 位于所述栅极绝缘层上并且具有与所述栅极绝缘膜的所述部分接触的第一表面和与所述第一表面相对的第二表面的栅电极; 覆盖栅电极的层间绝缘层; 和与杂质区接触的电极。 栅电极在垂直于半导体层的表面的栅电极的截面中具有与第二表面接触的角部的凹部。 由栅电极和层间绝缘层包围的空腔位于包括凹部的至少一部分的区域中。