公开(公告)号：US20210408934A1

公开(公告)日：2021-12-30

申请号：US17290489

申请日：2019-08-23

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yusuke KINOSHITA ,  Yasuhiro YAMADA ,  Takashi ICHIRYU ,  Masanori NOMURA ,  Hidetoshi ISHIDA

IPC: H02M7/483 ,  H02M1/08 ,  H01L29/778

Abstract: A GaN layer is formed over the substrate. An AlGaN layer is formed on the GaN layer. A first source electrode, a first gate electrode, a second gate electrode, and a second source electrode are formed on or over the AlGaN layer. A first p-type Alx1Ga1-x1N layer where 0≤x1

公开(公告)号：US20210134963A1

公开(公告)日：2021-05-06

申请号：US17256475

申请日：2019-06-12

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Masanori NOMURA ,  Hiroaki UENO ,  Yusuke KINOSHITA ,  Yasuhiro YAMADA ,  Hidetoshi ISHIDA

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/808 ,  H01L29/43

Abstract: A bidirectional switch element includes: a substrate; an AlzGa1-zN layer; an AlbGa1-bN layer; a first source electrode; a first gate electrode; a second gate electrode; a second source electrode; a p-type Alx1Ga1-x1N layer; a p-type Alx2Ga1-x2N layer; an AlyGa1-yN layer; and an AlwGa1-wN layer. The AlzGa1-zN layer is formed over the substrate. The AlbGa1-bN layer is formed on the AlzGa1-zN layer. The AlyGa1-yN layer is interposed between the substrate and the AlzGa1-zN layer. The AlwGa1-wN layer is interposed between the substrate and the AlyGa1-yN layer and has a higher C concentration than the AlyGa1-yN layer.

公开(公告)号：US20210265993A1

公开(公告)日：2021-08-26

申请号：US17256642

申请日：2019-06-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke KINOSHITA ,  Yasuhiro YAMADA ,  Hidekazu UMEDA

IPC: H03K17/56 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H02M7/537

Abstract: A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.

公开(公告)号：US20200027814A1

公开(公告)日：2020-01-23

申请号：US16497744

申请日：2018-03-27

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Takashi ICHIRYU ,  Masanori NOMURA ,  Yusuke KINOSHITA ,  Hidetoshi ISHIDA ,  Yasuhiro YAMADA

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532

Abstract: A semiconductor device includes a supporting substrate, a semiconductor chip, a resin member, and a heat-dissipating metal layer. The supporting substrate has a first surface and a second surface located opposite from each other in a thickness direction defined for the supporting substrate. The semiconductor chip includes a plurality of electrodes. The semiconductor chip is bonded to the supporting substrate on one side thereof with the first surface. The resin member has a first surface and a second surface located opposite from each other in a thickness direction defined for the resin member. The resin member covers at least a side surface of the supporting substrate and a side surface of the semiconductor chip. The heat-dissipating metal layer is arranged in contact with the supporting substrate and the resin member to cover the second surface of the supporting substrate and the second surface of the resin member at least partially.

公开(公告)号：US20150311331A1

公开(公告)日：2015-10-29

申请号：US14418589

申请日：2013-05-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yasuhiro YAMADA ,  Yoshiharu ANDA ,  Asamira SUZUKI

IPC: H01L29/778 ,  H01L29/205 ,  H01L23/00 ,  H01L21/285 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/417

CPC classification number: H01L29/7787 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02565 ,  H01L21/02579 ,  H01L21/28556 ,  H01L23/564 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/4966 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nitride semiconductor device of the present invention has a source-electrode-side insulator protection film layer disposed between a source electrode and a drain electrode on a second nitride semiconductor layer and formed at least partially covering the source electrode, a drain-electrode-side insulator protection film layer disposed separately from the source-electrode-side insulator protection film layer and formed at least partially covering the drain electrode, and a gate layer formed in contact with the second nitride semiconductor layer between the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and made of a p-type metal oxide semiconductor, and the gate layer has regions opposite to the second nitride semiconductor layer across each of the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and a region in contact with the second nitride semiconductor layer.

Abstract translation: 本发明的氮化物半导体器件具有源电极侧绝缘体保护膜层，其设置在第二氮化物半导体层上的源电极和漏电极之间，并且至少部分地覆盖源电极，漏电极侧 绝缘体保护膜层，与源电极侧绝缘体保护膜层分离设置，并形成为至少部分地覆盖漏极电极;以及栅极层，其与源极侧绝缘体保护膜之间的第二氮化物半导体层接触形成 层和漏电极侧绝缘体保护膜层，由p型金属氧化物半导体构成，栅极层具有穿过源电极侧绝缘体保护膜层和第二氮化物半导体层的与第二氮化物半导体层相反的区域 漏电极侧绝缘体保护膜层和与第二氮化物半导体接触的区域 ctor层。