公开(公告)号：US11171228B2

公开(公告)日：2021-11-09

申请号：US16708051

申请日：2019-12-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki Okita ,  Manabu Yanagihara ,  Masahiro Hikita

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/207 ,  H01L29/45 ,  H01L21/02 ,  H01L21/265

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer disposed above the substrate; a second nitride semiconductor layer disposed above the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a third nitride semiconductor layer selectively disposed above the second nitride semiconductor layer and containing a p-type first impurity element; a high resistance region disposed in the third nitride semiconductor layer, the high resistance region containing a second impurity element and having a specific resistance higher than a specific resistance of the third nitride semiconductor layer; and a gate electrode disposed above the high resistance region, wherein an end of the high resistance region is inside a surface end of the third nitride semiconductor layer.

公开(公告)号：US11257918B2

公开(公告)日：2022-02-22

申请号：US16723761

申请日：2019-12-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke Kanda ,  Hideyuki Okita ,  Manabu Yanagihara ,  Takeshi Harada

IPC: H01L29/778 ,  H01L29/45 ,  H01L21/285 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: A semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; an ohmic electrode above the substrate; and a contact layer in contact with at least a part of the ohmic electrode, the contact layer containing silicon and chlorine. The second nitride semiconductor layer has a wider band gap than the first nitride semiconductor layer. A two-dimensional electron gas channel is formed in the first nitride semiconductor layer at a heterointerface between the first nitride semiconductor layer and the second nitride semiconductor layer. A silicon concentration has a higher peak value than a chlorine concentration in the contact layer.

公开(公告)号：US09577084B2

公开(公告)日：2017-02-21

申请号：US14981831

申请日：2015-12-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masahiro Hikita ,  Hideyuki Okita

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/205 ,  H01L29/207 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a substrate, a semiconductor layer stacked body, and a source electrode and a drain electrode formed on the semiconductor layer stacked body. The semiconductor layer stacked body includes a first nitride semiconductor layer formed on the substrate, and a second nitride semiconductor layer formed on the first nitride semiconductor layer. The semiconductor device further includes a third nitride semiconductor layer formed on the second nitride semiconductor layer and disposed between the source electrode and the drain electrode, and a gate electrode formed on the third nitride semiconductor layer. The semiconductor device includes a first magnesium-containing region having a magnesium concentration of 1×1018 cm−3 or more that is provided right under the third nitride semiconductor layer, from an upper surface of the second nitride semiconductor layer to a position lower than an interface between the first nitride semiconductor layer and the second nitride semiconductor layer.

Abstract translation: 半导体器件包括衬底，半导体层堆叠体以及形成在半导体层堆叠体上的源电极和漏电极。 半导体层堆叠体包括形成在基板上的第一氮化物半导体层和形成在第一氮化物半导体层上的第二氮化物半导体层。 半导体器件还包括形成在第二氮化物半导体层上并且设置在源电极和漏电极之间的第三氮化物半导体层，以及形成在第三氮化物半导体层上的栅电极。 半导体器件包括第一含镁区域，其具有设置在第三氮化物半导体层正下方的1×10 18 cm -3以上的镁浓度，从第二氮化物半导体层的上表面到低于 第一氮化物半导体层和第二氮化物半导体层之间的界面。

公开(公告)号：US11152499B2

公开(公告)日：2021-10-19

申请号：US16575075

申请日：2019-09-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki Okita ,  Manabu Yanagihara ,  Takahiro Sato ,  Masahiro Hikita

IPC: H01L29/205 ,  H01L29/778 ,  H01L29/417 ,  H01L29/36 ,  H01L29/207 ,  H01L29/66 ,  H01L21/02 ,  H01L29/43 ,  H01L29/20 ,  H01L21/306 ,  H01L21/223 ,  H01L21/027

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer having a greater band gap than the first nitride semiconductor layer; a source electrode and a drain electrode on the second nitride semiconductor layer apart from each other; a third nitride semiconductor layer, between the source electrode and the drain electrode, containing a p-type first impurity and serving as a gate; and a fourth nitride semiconductor layer, between the third nitride semiconductor layer and the drain electrode, containing a p-type second impurity, wherein the average carrier concentration of the fourth nitride semiconductor layer is lower than the average carrier concentration of the third nitride semiconductor layer.

公开(公告)号：US20180248027A1

公开(公告)日：2018-08-30

申请号：US15958075

申请日：2018-04-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki Okita ,  Masahiro Hikita ,  Yasuhiro Uemoto

IPC: H01L29/778 ,  H01L29/808 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L27/098

CPC classification number: H01L29/7787 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/808

Abstract: A semiconductor device includes: a substrate; a channel layer constituted of a single nitride semiconductor on the substrate; a first barrier layer which is a nitride semiconductor on a part of an upper surface of the channel layer and having a band gap larger than that of the channel layer; a gate layer which is a nitride semiconductor on and in contact with the first barrier layer; a second barrier layer which is a nitride semiconductor in contact with the first barrier layer in an area where the gate layer is not disposed above the channel layer, and having a band gap larger than that of the channel layer and having a thickness or a band gap independent from the first barrier layer; a gate electrode on the gate layer; and a source electrode and a drain electrode spaced apart from the gate layer and on the second barrier layer.

公开(公告)号：US09412858B2

公开(公告)日：2016-08-09

申请号：US14983602

申请日：2015-12-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki Okita ,  Masahiro Hikita ,  Yasuhiro Uemoto

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7789 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787 ,  H01L29/7788

Abstract: A semiconductor device includes a substrate, a first nitride semiconductor layer formed on the substrate, a p-type nitride semiconductor layer formed on the first nitride semiconductor layer, a recess having a bottom portion which reaches the first nitride semiconductor layer through a part of the p-type nitride semiconductor layer, a third nitride semiconductor layer formed to cover the bottom portion of the recess, a side portion of the recess, and a part of an upper surface of the p-type nitride semiconductor layer. The semiconductor device further includes a fourth nitride semiconductor layer formed on the third nitride semiconductor layer, a first electrode formed on another side of the substrate, a gate electrode formed on the upper surface of the p-type nitride semiconductor layer, and a second electrode that is in contact with the third nitride semiconductor layer or the fourth nitride semiconductor layer. The third nitride semiconductor layer has a bandgap different from a bandgap of the fourth nitride semiconductor layer.

Abstract translation: 半导体器件包括衬底，形成在衬底上的第一氮化物半导体层，形成在第一氮化物半导体层上的p型氮化物半导体层，具有底部的凹部，该凹部通过部分第一氮化物半导体层到达第一氮化物半导体层 p型氮化物半导体层，形成为覆盖凹部的底部的第三氮化物半导体层，凹部的侧部以及p型氮化物半导体层的上表面的一部分。 半导体器件还包括形成在第三氮化物半导体层上的第四氮化物半导体层，形成在衬底的另一侧上的第一电极，形成在p型氮化物半导体层的上表面上的栅电极和第二电极 其与第三氮化物半导体层或第四氮化物半导体层接触。 第三氮化物半导体层具有与第四氮化物半导体层的带隙不同的带隙。

公开(公告)号：US09859413B2

公开(公告)日：2018-01-02

申请号：US15399443

申请日：2017-01-05

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Hideyuki Okita ,  Masahiro Hikita ,  Hisayoshi Matsuo ,  Yasuhiro Uemoto

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7787 ,  H01L29/0642 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/42316 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/7786

Abstract: A nitride semiconductor device including a substrate, a channel layer, a carbon-poor barrier layer having a recess, a carbon-rich barrier layer disposed over the recess and the carbon-poor barrier layer, and a gate electrode above the recess, wherein the carbon-poor and carbon-rich barrier layers have bandgaps larger than that of the channel layer, the upper surface of the carbon-rich barrier layer includes a first main surface including a source electrode and a drain electrode, and a bottom surface of a depression disposed along the recess, and side surfaces of the depression connecting the first main surface to the bottom surface of the depression, and among edges of the depression of the carbon-rich barrier layer which are boundaries between the first main surface and the side surfaces of the depression, the edge of the depression of the carbon-rich barrier layer closest to the drain electrode is covered with the gate electrode.