公开(公告)号：US20170345715A1

公开(公告)日：2017-11-30

申请号：US15594690

申请日：2017-05-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  SHOGO OKITA ,  AKIHIRO ITOU ,  KATSUMI TAKANO ,  MITSURU HIROSHIMA

IPC: H01L21/78 ,  H01L21/683 ,  H01L21/3065 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/3065 ,  H01L21/6836 ,  H01L24/11 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2224/13022

Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface provided with a bump and a second surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of adhering a protection tape having an adhesive layer to the first surface and embedding. The element chip manufacturing method includes a thinning process of grinding the second surface in a state where the protection tape is adhered to the first surface and thinning the substrate, after the bump embedding process, a mask forming process of forming a mask in the second surface and exposes the dividing regions, after the thinning process, a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape.

公开(公告)号：US20170345781A1

公开(公告)日：2017-11-30

申请号：US15594696

申请日：2017-05-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  SHOGO OKITA ,  AKIHIRO ITOU ,  KATSUMI TAKANO ,  MITSURU HIROSHIMA

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/687 ,  H01L21/67 ,  H01L21/48 ,  H05K13/04 ,  B44C1/22

CPC classification number: H01L24/11 ,  B44C1/227 ,  H01L21/4853 ,  H01L21/67069 ,  H01L21/68742 ,  H01L23/49811 ,  H01L24/13 ,  H01L2224/11 ,  H05K13/0465

Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface having an exposed bump and a second surface opposite to the first surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of embedding at least a head top part of the bump into the adhesive layer, a mask forming process of forming a mask in the second surface. The method for manufacturing the element chip includes a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape, a placement process of placing the substrate on a stage provided inside of a plasma processing apparatus through the holding tape, after the mask forming process and the holding process.