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1.发明申请LOW POWER RECEIVER FOR IMPLEMENTING A HIGH VOLTAGE INTERFACE IMPLEMENTED WITH LOW VOLTAGE DEVICES 有权用于实现低电压设备实现的高电压接口的低功率接收器公开(公告)号：US20130342258A1
公开(公告)日：2013-12-26
申请号：US13530426
申请日：2012-06-22
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K19/0013 , H03K19/018507
摘要： An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications.
摘要翻译： 一种包括第一级和第二级的装置。 第一级可以被配置为响应于具有从焊盘接收到的第二电压的输入信号而产生具有第一电压的中间信号。 第二级可以被配置为响应于第一电压而产生核心电压。 从焊盘接收的电压可以在符合一个或多个公布的接口规范的电压下工作。
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2.发明授权Low power receiver for implementing a high voltage interface implemented with low voltage devices 有权低功率接收器，用于实现采用低电压器件实现的高压接口公开(公告)号：US08847657B2
公开(公告)日：2014-09-30
申请号：US13530426
申请日：2012-06-22
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K19/0013 , H03K19/018507
摘要： An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications.
摘要翻译： 一种包括第一级和第二级的装置。 第一级可以被配置为响应于具有从焊盘接收到的第二电压的输入信号而产生具有第一电压的中间信号。 第二级可以被配置为响应于第一电压而产生核心电压。 从焊盘接收的电压可以在符合一个或多个公布的接口规范的电压下工作。
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3.发明授权AC noise suppression from a bias signal in high voltage supply/low voltage device 有权高压电源/低压器件偏置信号的交流噪声抑制公开(公告)号：US08487691B1
公开(公告)日：2013-07-16
申请号：US13494282
申请日：2012-06-12
IPC分类号： G05F1/10
CPC分类号： H03F1/26 , H03F3/2171 , H03K19/00346
摘要： An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first control voltage and a second control voltage. The second circuit may be configured to generate a bias signal in response to the first control voltage and the second control voltage. The third circuit may be configured to generate a filtered signal in response to the bias signal. The filtered signal may be added to the first control voltage and the second control voltage to provide AC noise suppression when generating the bias signal.
摘要翻译： 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以被配置为产生第一控制电压和第二控制电压。 第二电路可以被配置为响应于第一控制电压和第二控制电压而产生偏置信号。 第三电路可以被配置为响应于偏置信号产生滤波信号。 滤波后的信号可以被添加到第一控制电压和第二控制电压，以在产生偏置信号时提供AC噪声抑制。
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4.发明申请Interfacing between differing voltage level requirements in an integrated circuit system 审中-公开集成电路系统中不同电压等级要求之间的接口公开(公告)号：US20110102046A1
公开(公告)日：2011-05-05
申请号：US12610277
申请日：2009-10-31
申请人： PANKAJ KUMAR , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
发明人： PANKAJ KUMAR , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
IPC分类号： H03L5/00
CPC分类号： H03K19/00315
摘要： A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.
摘要翻译： 一种方法包括可控制地从电源电压产生第一偏置电压，使其处于集成电路的输入/输出（IO）核心器件的一个或多个构成的有源电路元件的工作电压的上容许限度内（ IC）与IO焊盘接口，并且可控制地从通过IO焊盘提供的外部电压产生第二偏置电压，使其在所述一个或多个构成的有源电路元件的工作电压的上容许限度内 要与IO接口连接的IO内核设备。 该方法还包括可控制地利用由IO核心产生的控制信号，以在驱动器操作模式期间从第一偏置电压导出输出偏置电压，或者在故障安全操作模式和容限操作模式期间导出第二偏置电压。
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5.发明申请BIAS VOLTAGE GENERATION TO PROTECT INPUT/OUTPUT (IO) CIRCUITS DURING A FAILSAFE OPERATION AND A TOLERANT OPERATION 有权偏置电压发生保护输入/输出（IO）电路在故障安全操作和容错操作公开(公告)号：US20110102048A1
公开(公告)日：2011-05-05
申请号：US12889440
申请日：2010-09-24
申请人： Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
发明人： Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
IPC分类号： H03L5/00
CPC分类号： H03K19/00315
摘要： A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.
摘要翻译： 一种方法包括可控制地从电源电压产生第一偏置电压，使其处于集成电路的输入/输出（IO）核心器件的一个或多个构成的有源电路元件的工作电压的上容许限度内（ IC）与IO焊盘接口，并且可控制地从通过IO焊盘提供的外部电压产生第二偏置电压，使其在所述一个或多个构成的有源电路元件的工作电压的上容许限度内 要与IO接口连接的IO内核设备。 该方法还包括可控制地利用由IO核心产生的控制信号，以在驱动器操作模式期间从第一偏置电压导出输出偏置电压，或者在故障安全操作模式和容限操作模式期间导出第二偏置电压。
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6.发明授权Floating well circuit operable in a failsafe condition and a tolerant condition 有权浮动井回路可在故障安全条件和容限条件下工作公开(公告)号：US07876132B1
公开(公告)日：2011-01-25
申请号：US12580280
申请日：2009-10-16
申请人： Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
发明人： Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
IPC分类号： H03B1/00
CPC分类号： H03K17/08104 , H03K17/063 , H03K19/00315 , H03K2217/0018
摘要： A circuit includes a first comparator block configured to output a voltage equal to a higher of a supply voltage and a bias voltage, a second comparator block configured to output a voltage equal to a higher of the bias voltage and an external voltage supplied through an Input/Output (IO) pad, and a third comparator block configured to output a voltage equal to a higher of the output of the first comparator block and the output of the second comparator block. A voltage across one or more constituent active element(s) of each of the first comparator block, the second comparator block, and the third comparator block is within an upper tolerable limit thereof during each of a normal operation, a failsafe operation, and a tolerant operation.
摘要翻译： 电路包括：第一比较器块，被配置为输出等于较高的电源电压和偏置电压的电压;第二比较器块，被配置为输出等于较高偏置电压的电压和通过输入提供的外部电压 /输出（IO）焊盘和第三比较器块，其被配置为输出等于第一比较器块的输出的较高的电压和第二比较器块的输出。 第一比较器块，第二比较器块和第三比较器块中的每个的一个或多个构成有源元件上的电压在正常操作，故障安全操作和 容忍操作。
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7.发明授权Interfacing between differing voltage level requirements in an integrated circuit system 有权集成电路系统中不同电压等级要求之间的接口公开(公告)号：US08130030B2
公开(公告)日：2012-03-06
申请号：US12610276
申请日：2009-10-31
申请人： Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
发明人： Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
IPC分类号： G05F1/10
CPC分类号： H03K17/693 , H03K19/00315 , H03K19/007
摘要： A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an IO receiver, and controllably generating a second bias voltage from an external voltage supplied through an IO pad to be within the upper tolerable limit of the operating voltage of the IO receiver. The method also includes deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, and deriving the output voltage from the second bias voltage during a failsafe condition. The tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and the failsafe condition is a mode of operation where the supply voltage is zero.
摘要翻译： 一种方法包括可控制地从电源电压产生第一偏置电压，使其在IO接收器的工作电压的上限允许极限内，并且可控制地从通过IO焊盘提供的外部电压产生第二偏置电压以在上部 IO接收器的工作电压允许限制。 该方法还包括在正常条件和容限条件期间从第一偏置电压导出输出电压，以及在故障安全状态期间从第二偏置电压导出输出电压。 容许条件是通过IO垫提供的外部电压从零变化到高于电源电压的值的操作模式，并且故障保护条件是电源电压为零的操作模式。
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8.发明授权Bias voltage generation to protect input/output (IO) circuits during a failsafe operation and a tolerant operation 有权偏置电压产生，用于在故障安全操作和容错操作期间保护输入/输出（IO）电路公开(公告)号：US08125267B2
公开(公告)日：2012-02-28
申请号：US12889440
申请日：2010-09-24
IPC分类号： G05F1/10
CPC分类号： H03K19/00315
摘要： A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.
摘要翻译： 一种方法包括可控制地从电源电压产生第一偏置电压，使其处于集成电路的输入/输出（IO）核心器件的一个或多个构成的有源电路元件的工作电压的上容许限度内（ IC）与IO焊盘接口，并且可控制地从通过IO焊盘提供的外部电压产生第二偏置电压，使其在所述一个或多个构成的有源电路元件的工作电压的上容许限度内 要与IO接口连接的IO内核设备。 该方法还包括可控制地利用由IO核心产生的控制信号，以在驱动器操作模式期间从第一偏置电压导出输出偏置电压，或者在故障安全操作模式和容限操作模式期间导出第二偏置电压。
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9.发明申请INTERFACING BETWEEN DIFFERING VOLTAGE LEVEL REQUIREMENTS IN AN INTEGRATED CIRCUIT SYSTEM 有权集成电路系统中不同电压等级要求之间的接口公开(公告)号：US20110102045A1
公开(公告)日：2011-05-05
申请号：US12610276
申请日：2009-10-31
申请人： PANKAJ KUMAR , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
发明人： PANKAJ KUMAR , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
IPC分类号： H03L5/00
CPC分类号： H03K17/693 , H03K19/00315 , H03K19/007
摘要： A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an IO receiver, and controllably generating a second bias voltage from an external voltage supplied through an IO pad to be within the upper tolerable limit of the operating voltage of the IO receiver. The method also includes deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, and deriving the output voltage from the second bias voltage during a failsafe condition. The tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and the failsafe condition is a mode of operation where the supply voltage is zero.
摘要翻译： 一种方法包括可控制地从电源电压产生第一偏置电压，使其在IO接收器的工作电压的上限允许极限内，并且可控制地从通过IO焊盘提供的外部电压产生第二偏置电压以在上部 IO接收器的工作电压允许限制。 该方法还包括在正常条件和容限条件期间从第一偏置电压导出输出电压，以及在故障安全状态期间从第二偏置电压导出输出电压。 容许条件是通过IO垫提供的外部电压从零变化到高于电源电压的值的操作模式，并且故障保护条件是电源电压为零的操作模式。
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公开(公告)号：US07834653B1
公开(公告)日：2010-11-16
申请号：US12610275
申请日：2009-10-31
IPC分类号： H03K19/007
CPC分类号： H03K19/00315 , H03K17/08104 , H03K19/007
摘要： A method includes controllably utilizing a control signal generated by an Input/Output (IO) core to isolate a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a number of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof during a failsafe mode of operation and a tolerant mode of operation. The method also includes feeding back an appropriate voltage to a floating node created by the isolation of the current path, and controlling a voltage across each transistor of the number of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor derived from the supply voltage or the external voltage supplied through the IO pad.
摘要翻译： 一种方法包括可控地利用由输入/输出（IO）芯产生的控制信号，以将电流路径与通过IO垫提供的外部电压隔离成电源电压，通过在晶体管的输入端发送相同的电压，配置 作为接口电路的IO驱动器的多个级联晶体管的一部分，在故障安全操作模式和容限操作模式期间连接到其输出端子。 该方法还包括将适当的电压反馈到通过隔离电流路径而产生的浮动节点，并且通过施加栅极电压来控制级联晶体管数量的每个晶体管上的电压在其可容许的上限范围内 到源于通过IO焊盘提供的电源电压或外部电压的每个晶体管。
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