公开(公告)号：US5732012A

公开(公告)日：1998-03-24

申请号：US210595

申请日：1994-03-17

申请人： Paolo Cappelletti ,  Silvia Lucherini ,  Bruno Vajana

发明人： Paolo Cappelletti ,  Silvia Lucherini ,  Bruno Vajana

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  G11C17/12

CPC分类号： H01L27/11253 ,  H01L27/112 ,  H01L27/1126 ,  H01L27/11266

摘要： A ROM cell array in which the drains are more lightly doped than the sources. This reduces the worst-case capacitance seen by the bitlines, and consequently reduces the access time of the memory.

摘要翻译： 一个ROM单元阵列，其中漏极比源轻掺杂。 这减少了位线所看到的最坏情况电容，从而减少了存储器的访问时间。

公开(公告)号：US5328863A

公开(公告)日：1994-07-12

申请号：US668873

申请日：1991-03-13

申请人： Paolo Cappelletti ,  Silvia Lucherini ,  Bruno Vajana

发明人： Paolo Cappelletti ,  Silvia Lucherini ,  Bruno Vajana

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11253 ,  H01L27/112 ,  H01L27/1126 ,  H01L27/11266

摘要： A process which provides for the creation of regions of source and drain having different doping, wherein the doping, and thus the capacitance, of the drain regions is lower than that of the source regions.

摘要翻译： 提供了产生具有不同掺杂的源极和漏极的区域的工艺，其中漏极区域的掺杂以及因此的电容低于源极区域的掺杂。

公开(公告)号：US5486487A

公开(公告)日：1996-01-23

申请号：US139800

申请日：1993-10-19

申请人： Giancarlo Ginami ,  Enrico Laurin ,  Silvia Lucherini ,  Bruno Vajana

发明人： Giancarlo Ginami ,  Enrico Laurin ,  Silvia Lucherini ,  Bruno Vajana

IPC分类号： G11C17/12 ,  H01L27/112 ,  H01L21/266

CPC分类号： H01L27/112 ,  G11C17/12

摘要： A method of manufacture of a low-capacitance programmed cell structure for read-only memory circuits comprises a field-effect transistor having conventional source and drain regions separated by a channel region overlaid by the gate of the transistor. This ROM memory cell is programmed by a channel implant extending only from the source region for a selected distance into the channel region.

摘要翻译： 制造用于只读存储器电路的低电容编程单元结构的方法包括具有由晶体管的栅极重叠的沟道区隔开的常规源极和漏极区域的场效应晶体管。 该ROM存储器单元通过仅从源极区域延伸一个选定距离进入沟道区域的沟道注入来编程。

公开(公告)号：US5597750A

公开(公告)日：1997-01-28

申请号：US474735

申请日：1995-06-07

申请人： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

发明人： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  G11C16/04 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11541

摘要： A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit lines, moreover, are gathered into groups or bytes of simultaneously addressable adjacent lines. Each cell in the matrix incorporates a floating gate transistor which is coupled to a control gate, connected to the control gate line, and is connected serially to a selection transistor; also, the cells of each individual byte share their respective source areas, which areas are structurally independent for each byte and are led to a corresponding source addressing line extending along a matrix column.

摘要翻译： 一种用于EEPROM存储器单元的矩阵的电路结构，其包括包括多行和列的单元矩阵，每行具有字线和控制栅极线，每列具有位线; 此外，位线被收集成同时可寻址的相邻线的组或字节。 矩阵中的每个单元都包含一个浮动栅极晶体管，它连接到控制栅极，连接到控制栅极线，并串联连接到选择晶体管; 每个单独字节的单元也共享它们各自的源区域，哪些区域对于每个字节在结构上是独立的，并且被引导到沿着矩阵列延伸的对应的源寻址行。

公开(公告)号：US5677871A

公开(公告)日：1997-10-14

申请号：US688233

申请日：1996-07-29

申请人： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

发明人： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  G11C16/04 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11541

摘要： A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit lines, moreover, are gathered into groups or bytes of simultaneously addressable adjacent lines. Each cell in the matrix incorporates a floating gate transistor which is coupled to a control gate, connected to the control gate line, and is connected serially to a selection transistor; also, the cells of each individual byte share their respective source areas, which areas are structurally independent for each byte and are led to a corresponding source addressing line extending along a matrix column.

摘要翻译： 一种用于EEPROM存储器单元的矩阵的电路结构，其包括包括多行和列的单元矩阵，每行具有字线和控制栅极线，每列具有位线; 此外，位线被收集成同时可寻址的相邻线的组或字节。 矩阵中的每个单元都包含一个浮动栅极晶体管，它连接到控制栅极，连接到控制栅极线，并串联连接到选择晶体管; 每个单独字节的单元也共享它们各自的源区域，哪些区域对于每个字节在结构上是独立的，并且被引导到沿着矩阵列延伸的对应的源寻址行。