公开(公告)号：US20100221848A1

公开(公告)日：2010-09-02

申请号：US12778725

申请日：2010-05-12

Applicant: Parviz KESHTBOD ,  Ebrahim ABEDIFARD

Inventor： Parviz KESHTBOD ,  Ebrahim ABEDIFARD

IPC: H01L21/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/105 ,  H01L27/228

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract translation: 磁性随机存取存储器（MRAM）单元包括嵌入式MRAM和存取晶体管。 嵌入式MRAM形成在多个金属插入层间电介质（ILD）层中，每个层包括分散在其中的金属并形成在存取晶体管的顶部。 在位于靠近位线的ILD层中形成的金属的顶部上形成磁隧道结（MTJ）。 MTJ掩模用于对MTJ进行图案蚀刻，以暴露MTJ。 最终，在位线顶部形成金属并延伸以接触MTJ。

公开(公告)号：US20130017627A1

公开(公告)日：2013-01-17

申请号：US13623054

申请日：2012-09-19

Applicant: Parviz KESHTBOD ,  Ebrahim ABEDIFARD

Inventor： Parviz KESHTBOD ,  Ebrahim ABEDIFARD

IPC: H01L43/12

CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/105 ,  H01L27/228

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract translation: 磁性随机存取存储器（MRAM）单元包括嵌入式MRAM和存取晶体管。 嵌入式MRAM形成在多个金属插入层间电介质（ILD）层中，每个层包括分散在其中的金属并形成在存取晶体管的顶部。 在位于靠近位线的ILD层中形成的金属的顶部上形成磁隧道结（MTJ）。 MTJ掩模用于对MTJ进行图案蚀刻，以暴露MTJ。 最终，在位线顶部形成金属并延伸以接触MTJ。

公开(公告)号：US20100259976A1

公开(公告)日：2010-10-14

申请号：US12756081

申请日：2010-04-07

Applicant: Ebrahim ABEDIFARD

Inventor： Ebrahim ABEDIFARD

IPC: G11C11/14 ,  G11C11/416

CPC classification number: G11C8/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C2213/75

Abstract: A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.

Abstract translation: 公开了一种自旋转矩传递存储器随机存取存储器（STTMRAM）单元，其包括被识别为被编程的所选择的磁性隧道结（MTJ）; 具有第一端口，第二端口和栅极的第一晶体管，耦合到所选择的MTJ的第一晶体管的第一端口; 通过第一晶体管的第二端口耦合到所选择的MTJ的第一相邻MTJ; 具有第一端口，第二端口和栅极的第二晶体管，耦合到所选择的MTJ的第二晶体管的第一端口; 通过第二晶体管的第二端口耦合到所选择的MTJ的第二相邻MTJ; 耦合到所选MTJ的第二端的第一位/源极线; 以及耦合到第一相邻MTJ的第二端和第二相邻MTJ的第二端的第二位/源极线。

公开(公告)号：US20120230101A1

公开(公告)日：2012-09-13

申请号：US13481097

申请日：2012-05-25

Applicant: Ebrahim ABEDIFARD ,  Petro ESTAKHRI

Inventor： Ebrahim ABEDIFARD ,  Petro ESTAKHRI

IPC: G11C11/14

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/5607

Abstract: A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.

Abstract translation: 写入磁存储器阵列的磁隧道结（MTJ）的方法包括将缓存数据存储在高速缓存寄存器中，读取至少两个MTJ的集合中的第一个的当前逻辑状态，该集合至少 两个MTJ，包括第一个MTJ和第二个MTJ。 即将发送的数据将被写入第二个MTJ。 进一步的步骤是将读逻辑状态存储到数据寄存器中，交换数据寄存器和高速缓存寄存器的内容，使得高速缓存寄存器存储读逻辑状态，数据寄存器存储进来数据，施加第一预定电压 电平到MTJ集合，从而使第一MTJ被重写，向MTJ集合施加第二预定电压电平，并将进入的数据存储到第二MTJ中。

公开(公告)号：US20160118102A1

公开(公告)日：2016-04-28

申请号：US14754635

申请日：2015-06-29

Applicant: Ebrahim ABEDIFARD ,  Petro ESTAKHRI

Inventor： Ebrahim ABEDIFARD ,  Petro ESTAKHRI

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/5607

Abstract: A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.

Abstract translation: 写入磁存储器阵列的磁隧道结（MTJ）的方法包括将缓存数据存储在高速缓存寄存器中，读取至少两个MTJ的集合中的第一个的当前逻辑状态，该集合至少 两个MTJ，包括第一个MTJ和第二个MTJ。 即将发送的数据将被写入第二个MTJ。 进一步的步骤是将读逻辑状态存储到数据寄存器中，交换数据寄存器和高速缓存寄存器的内容，使得高速缓存寄存器存储读逻辑状态，数据寄存器存储进来数据，施加第一预定电压 电平到MTJ集合，从而使第一MTJ被重写，向MTJ集合施加第二预定电压电平，并将进入的数据存储到第二MTJ中。

公开(公告)号：US20110249491A1

公开(公告)日：2011-10-13

申请号：US12826546

申请日：2010-06-29

Applicant: Ebrahim ABEDIFARD ,  Petro ESTAKHRI

Inventor： Ebrahim ABEDIFARD ,  Petro ESTAKHRI

IPC: G11C11/14 ,  G11C7/00

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/5607

Abstract: A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.

Abstract translation: 写入磁存储器阵列的磁隧道结（MTJ）的方法包括将缓存数据存储在高速缓存寄存器中，读取至少两个MTJ的集合中的第一个的当前逻辑状态，该集合至少 两个MTJ，包括第一个MTJ和第二个MTJ。 即将发送的数据将被写入第二个MTJ。 进一步的步骤是将读逻辑状态存储到数据寄存器中，交换数据寄存器和高速缓存寄存器的内容，使得高速缓存寄存器存储读逻辑状态，数据寄存器存储进来数据，施加第一预定电压 电平到MTJ集合，从而使第一MTJ被重写，向MTJ集合施加第二预定电压电平，并将进入的数据存储到第二MTJ中。

公开(公告)号：US20100315870A1

公开(公告)日：2010-12-16

申请号：US12860793

申请日：2010-08-20

Applicant: Ebrahim ABEDIFARD

Inventor： Ebrahim ABEDIFARD

IPC: G11C11/14

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/5607

Abstract: A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor.

Abstract translation: 写入磁存储器阵列的磁性隧道结（MTJ）的方法包括耦合到MTJ的访问晶体管，用于读取和写入MTJ，其中当MTJ被写入时，通过切换其磁性取向 从反并联到并行磁取向，耦合到MTJ的一端的位线被提升到Vcc，并且作为Vcc和Vx之和的电压被施加到存取晶体管的栅极，Vx 大约是MTJ相对端的电压。 此外，使用也耦合到SL的写入驱动器的第一晶体管耦合到MTJ的源极线（SL）的电压被调节，使得SL保持足够高于0伏，以避免超过Vgs的超出 Vcc，其中Vgs是存取晶体管的源极电压的栅极。