公开(公告)号：US20100221848A1

公开(公告)日：2010-09-02

申请号：US12778725

申请日：2010-05-12

Applicant: Parviz KESHTBOD ,  Ebrahim ABEDIFARD

Inventor： Parviz KESHTBOD ,  Ebrahim ABEDIFARD

IPC: H01L21/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/105 ,  H01L27/228

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract translation: 磁性随机存取存储器（MRAM）单元包括嵌入式MRAM和存取晶体管。 嵌入式MRAM形成在多个金属插入层间电介质（ILD）层中，每个层包括分散在其中的金属并形成在存取晶体管的顶部。 在位于靠近位线的ILD层中形成的金属的顶部上形成磁隧道结（MTJ）。 MTJ掩模用于对MTJ进行图案蚀刻，以暴露MTJ。 最终，在位线顶部形成金属并延伸以接触MTJ。

公开(公告)号：US20130017627A1

公开(公告)日：2013-01-17

申请号：US13623054

申请日：2012-09-19

Applicant: Parviz KESHTBOD ,  Ebrahim ABEDIFARD

Inventor： Parviz KESHTBOD ,  Ebrahim ABEDIFARD

IPC: H01L43/12

CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/105 ,  H01L27/228

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract translation: 磁性随机存取存储器（MRAM）单元包括嵌入式MRAM和存取晶体管。 嵌入式MRAM形成在多个金属插入层间电介质（ILD）层中，每个层包括分散在其中的金属并形成在存取晶体管的顶部。 在位于靠近位线的ILD层中形成的金属的顶部上形成磁隧道结（MTJ）。 MTJ掩模用于对MTJ进行图案蚀刻，以暴露MTJ。 最终，在位线顶部形成金属并延伸以接触MTJ。

公开(公告)号：US20120107964A1

公开(公告)日：2012-05-03

申请号：US13345608

申请日：2012-01-06

Applicant: Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Mahmud ASSAR

Inventor： Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Mahmud ASSAR

IPC: H01L21/8239

CPC classification number: G06F12/0246 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C14/00 ,  H01L27/105 ,  H01L27/224

Abstract: A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

Abstract translation: 闪存RAM存储器的方法包括形成在单片模块上的非易失性随机存取存储器（RAM）和形成在非易失性RAM，非易失性页面模式存储器和非易失性页面模式存储器之上的非易失性页面模式存储器 非易失性RAM驻留在单片芯片上。 非易失性RAM由以三维形式布置的磁存储单元堆叠形成，用于更高密度和更低成本。

公开(公告)号：US20080293165A1

公开(公告)日：2008-11-27

申请号：US12040827

申请日：2008-02-29

Applicant: Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Roger Klas MALMHALL

Inventor： Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Roger Klas MALMHALL

IPC: H01L21/00

CPC classification number: H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/16 ,  H01L27/228

Abstract: In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.

Abstract translation: 根据本发明的方法，公开了一种制造磁随机存取存储器（MRAM）单元及其相应结构的方法，以包括多级制造工艺。 多级制造过程包括通过形成中间层间电介质（ILD）层来形成前端在线（FEOL）级来制造存储单元的逻辑和非磁性部分，形成嵌入在中间ILD中的中间金属柱 层，在中间ILD层和金属柱的顶部上沉积导电金属帽，进行磁性制造阶段以制造存储单元的磁性材料部分，并执行后端在线（BEOL）阶段以制造金属 和正在制造的存储单元的触点。

公开(公告)号：US20090154229A1

公开(公告)日：2009-06-18

申请号：US12125866

申请日：2008-05-22

Applicant: Parviz KESHTBOD

Inventor： Parviz KESHTBOD

IPC: G11C11/14 ,  G11C7/00 ,  G11C11/416

CPC classification number: G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693

Abstract: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.

Abstract translation: 感测电路包括具有第一和第二节点的读出放大器电路，通过该第一和第二节点检测磁存储元件。 第一电流源耦合到第一节点，第二电流源耦合到第二节点。 参考磁存储元件具有与之相关联的电阻并且耦合到第一节点，参考磁存储元件从第一电流源接收电流。 具有与其相关联的电阻的至少一个存储元件耦合到第二节点并从第二电流源接收电流。 来自第一电流源的电流和来自第二电流源的电流基本上相同。 通过比较至少一个存储元件的电阻与参考磁存储元件的电阻来感测至少一个存储元件的逻辑状态。

公开(公告)号：US20090046501A1

公开(公告)日：2009-02-19

申请号：US12182996

申请日：2008-07-30

Applicant: Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Mahmud ASSAR

Inventor： Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Mahmud ASSAR

IPC: G11C11/14 ,  H01L21/00 ,  G11C11/34

CPC classification number: G06F12/0246 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C14/00 ,  H01L27/105 ,  H01L27/224

Abstract: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die.

Abstract translation: 闪存RAM存储器包括形成在单片模块上的非易失性随机存取存储器（RAM）和形成在非易失性RAM，非易失性页面模式存储器和非易失性页面模式存储器之上的非易失性页面模式存储器， 易失性RAM驻留在单片模具上。

公开(公告)号：US20110096593A1

公开(公告)日：2011-04-28

申请号：US12985028

申请日：2011-01-05

Applicant: Rajiv Yadav RANJAN ,  Roger Klas MALMHALL ,  Parviz KESHTBOD

Inventor： Rajiv Yadav RANJAN ,  Roger Klas MALMHALL ,  Parviz KESHTBOD

IPC: G11C11/15

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  H01L43/08

Abstract: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

公开(公告)号：US20080164548A1

公开(公告)日：2008-07-10

申请号：US12040801

申请日：2008-02-29

Applicant: Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Roger Klas MALMHALL

Inventor： Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Roger Klas MALMHALL

IPC: H01L29/82 ,  H01L21/00

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  H01L43/08

Abstract: One embodiment of the present invention includes a non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, and a free layer formed on top of the barrier layer, wherein the electrical resistivity of the barrier layer is reduced by placing said barrier layer under compressive stress. Compressive stress is induced by either using a compressive stress inducing layer, or by using inert gases at low pressure during the sputtering process as the barrier layer is deposited, or by introducing compressive stress inducing molecules into the molecular lattice of the barrier layer.

Abstract translation: 本发明的一个实施例包括非易失性磁存储元件，其包括固定层，形成在固定层顶部上的阻挡层和形成在阻挡层顶部上的自由层，其中势垒层的电阻率 通过将所述阻挡层置于压应力下来减少。 或者通过使用压缩应力诱导层或在溅射过程中使用惰性气体在溅射过程中作为阻挡层被沉积或通过将压应力诱导分子引入到阻挡层的分子晶格中而引起压缩应力。

公开(公告)号：US20110103143A1

公开(公告)日：2011-05-05

申请号：US12986802

申请日：2011-01-07

Applicant: Rajiv Yadav RANJAN ,  Roger Klas MALMHALL ,  Parviz KESHTBOD

Inventor： Rajiv Yadav RANJAN ,  Roger Klas MALMHALL ,  Parviz KESHTBOD

IPC: G11C11/14 ,  H01L29/82

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

Abstract translation: 公开了一种包括自由层，两个堆叠和磁性隧道结的多状态低电流切换磁存储元件（磁存储元件）。 堆叠和磁性隧道结设置在自由层的表面上，磁性隧道结位于堆叠之间。 堆叠在自由层内引导磁畴，产生自由层畴壁。 从堆栈传递到堆栈的电流推动域壁，重新定位自由层内的域壁。 畴壁相对于磁性隧道结的位置对应于唯一的电阻值，并且将电流从堆叠传递到磁性隧道结读取磁存储元件的电阻。 因此，可以通过移动域壁来实现唯一的记忆状态。

公开(公告)号：US20110089511A1

公开(公告)日：2011-04-21

申请号：US12975304

申请日：2010-12-21

Applicant: Parviz KESHTBOD ,  Roger Klas MALMHALL ,  Rajiv Yadav RANJAN

Inventor： Parviz KESHTBOD ,  Roger Klas MALMHALL ,  Rajiv Yadav RANJAN

IPC: H01L29/82 ,  H01L21/8246

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.

Abstract translation: 制造磁性随机存取存储单元的方法包括在晶片的顶部形成磁性隧道结（MTJ），在MTJ的顶部上沉积氧化物，在氧化物层的顶部上沉积光致抗蚀剂层，形成沟槽 所述光刻胶层和所述沟槽的宽度与所述MTJ的宽度基本相同的氧化物层。 然后，除去光致抗蚀剂层，并且在沟槽中的氧化物层的顶部上沉积硬掩模层，并且平坦化晶片以去除不在沟槽中的硬掩模层的部分以使顶部基本上平坦 的氧化物层和硬质层。 蚀刻剩余的氧化物层，并蚀刻MTJ以除去未被硬掩模层覆盖的MTJ的部分。