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1.发明授权Method and circuits to virtually increase the number of prototypes in artificial neural networks 失效实际增加人造神经网络中原型数量的方法和电路公开(公告)号：US07254565B2
公开(公告)日：2007-08-07
申请号：US10137969
申请日：2002-05-03
CPC分类号： G06K9/6276 , G06N3/063
摘要： An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a prototype and a distance evaluator to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The database block has: all the prototypes arranged in slices, each slice being capable to store up to a maximum number of prototypes; the input patterns or queries to be presented to the ANN; and the distances resulting of the evaluation performed during the recognition/classification phase. The compare and update circuit compares the distance with the distance previously found for the same input pattern updates or not the distance previously stored.
摘要翻译： 公开了一种改进的人造神经网络（ANN），其包括常规ANN，数据库块以及比较和更新电路。 常规ANN由多个神经元形成，每个神经元具有专用于存储原型的原型存储器和距离评估器，以评估呈现给ANN的输入模式与存储在其中的原型之间的距离。 数据库块具有：所有原型以切片排列，每个切片能够存储最多数量的原型; 要呈现给ANN的输入模式或查询; 以及在识别/分类阶段期间进行评估的距离。 比较和更新电路将距离与先前发现的相同输入模式更新的距离进行比较，或将之前存储的距离进行比较。
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2.发明授权Circuits and method for shaping the influence field of neurons and neural networks resulting therefrom 失效用于形成由此产生的神经元和神经网络的影响场的电路和方法公开(公告)号：US06347309B1
公开(公告)日：2002-02-12
申请号：US09223478
申请日：1998-12-30
IPC分类号： G06N306
CPC分类号： G06K9/6271 , G06N3/063
摘要： The improved neural network of the present invention results from the combination of a dedicated logic block with a conventional neural network based upon a mapping of the input space usually employed to classify an input data by computing the distance between said input data and prototypes memorized therein. The improved neural network is able to classify an input data, for instance, represented by a vector A even when some of its components are noisy or unknown during either the learning or the recognition phase. To that end, influence fields of various and different shapes are created for each neuron of the conventional neural network. The logic block transforms at least some of the n components (A1, . . . , An) of the input vector A into the m components (V1, . . . , Vm) of a network input vector V according to a linear or non-linear transform function F. In turn, vector V is applied as the input data to said conventional neural network. The transform function F is such that certain components of vector V are not modified, e.g. Vk=Aj, while other components are transformed as mentioned above, e.g. Vi=Fi(A1, . . . , An). In addition, one (or more) component of vector V can be used to compensate an offset that is present in the distance evaluation of vector V. Because, the logic block is placed in front of the said conventional neural network any modification thereof is avoided.
摘要翻译： 本发明的改进的神经网络是基于通常用于通过计算所述输入数据与其中存储的原型之间的距离来对输入数据进行分类的输入空间的映射，将专用逻辑块与传统神经网络的组合。 改进的神经网络能够对例如由向量A表示的输入数据进行分类，即使在学习或识别阶段期间，其一些组件是噪声或未知的。 为此，为传统神经网络的每个神经元创建各种不同形状的影响场。 逻辑块根据线性或非线性将输入矢量A的n个分量（A1，...，An）中的至少一些变换成网络输入矢量V的m个分量（V1，...，Vm） 然后将矢量V作为输入数据施加到所述常规神经网络。 变换函数F使得向量V的某些分量不被修改，例如， Vk = Aj，而其它组分如上所述被转化，例如。 Vi = Fi（A1，...，An）。 另外，矢量V的一个（或多个）分量可以用于补偿矢量V的距离评估中存在的偏移。因为逻辑块被放置在所述传统神经网络的前面，所以避免了其任何修改 。
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3.发明授权Method and circuits for associating a complex operator to each component of an input pattern presented to an artificial neural network 失效用于将复杂算子与呈现给人造神经网络的输入模式的每个分量相关联的方法和电路公开(公告)号：US08027942B2
公开(公告)日：2011-09-27
申请号：US09951786
申请日：2001-09-12
CPC分类号： G06K9/6215 , G06K9/6276 , G06N3/063
摘要： The method and circuits of the present invention aim to associate a complex component operator (CC_op) to each component of an input pattern presented to an input space mapping algorithm based artificial neural network (ANN) during the distance evaluation process. A complex operator consists in the description of a function and a set of parameters attached thereto. The function is a mathematical entity (either a logic operator e.g. match(Ai,Bi), abs(Ai−Bi), . . . or an arithmetic operator, e.g. >,
摘要翻译： 本发明的方法和电路旨在将复杂分量算子（CC_op）与在距离评估过程中呈现给基于输入空间映射算法的人造神经网络（ANN）的输入模式的每个分量相关联。 复杂的运算符在于对附加到其上的函数和一组参数的描述。 该函数是数学实体（逻辑运算符，例如匹配（Ai，Bi），abs（Ai-Bi），...或算术运算符，例如>，<，...。）或一组软件指令 有条件。 在第一实施例中，ANN被提供有存储所有CC_ops的ANN的所有神经元共用的全局存储器。 在另一个实施例中，CC_ops的集合存储在神经元的原型存储器中，使得全局存储器不再是物理上必需的。 根据本发明，存储的原型的组件现在可以指定不同性质的对象。 另外，这两种实现都显着减少神经元所需的组件数量，从而在ANN集成在硅芯片中时节省空间。
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公开(公告)号：US07133854B2
公开(公告)日：2006-11-07
申请号：US10014166
申请日：2001-12-11
CPC分类号： G06T9/00
摘要： Let us consider a plurality of input patterns having an essential characteristic in common but which differ on at least one parameter (this parameter modifies the input pattern in some extent but not this essential characteristic for a specific application). During the learning phase, each input pattern is normalized in a normalizer, before it is presented to a classifier. If not recognized, it is learned, i.e. the normalized pattern is stored in the classifier as a prototype with its category associated thereto. From a predetermined reference value of that parameter, the normalizer computes an element related to said parameter which allows to set the normalized pattern from the input pattern and vice versa to retrieve the input pattern from the normalized pattern. As a result, all these input patterns are represented by the same normalized pattern. The above method and circuits allow to reduce the number of required prototypes in the classifier, improving thereby its response quality.
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5.发明授权Method to improve the data transfer rate between a computer and a neural network 失效提高计算机和神经网络之间数据传输速率的方法公开(公告)号：US06983265B2
公开(公告)日：2006-01-03
申请号：US10316250
申请日：2002-12-10
IPC分类号： G06N3/06
CPC分类号： G06K9/6276 , G06N3/04
摘要： A method is described to improve the data transfer rate between a personal computer or a host computer and a neural network implemented in hardware by merging a plurality of input patterns into a single input pattern configured to globally represent the set of input patterns. A base consolidated vector (U′*n) representing the input pattern is defined to describe all the vectors (Un, . . . , Un+6) representing the input patterns derived thereof (U′n, . . . , U′n+6) by combining components having fixed and ‘don't care’ values. The base consolidated vector is provided only once with all the components of the vectors. An artificial neural network (ANN) is then configured as a combination of sub-networks operating in parallel. In order to compute the distances with an adequate number of components, the prototypes are to include also components having a definite value and ‘don't care’ conditions. During the learning phase, the consolidated vectors are stored as prototypes. During the recognition phase, when a new base consolidated vector is provided to ANN, each sub-network analyses a portion thereof After computing all the distances, they are sorted one sub-network at a time to obtain the distances associated to each vector.
摘要翻译： 描述了一种方法，以通过将多个输入模式合并为被配置为全局地表示该组输入模式的单个输入模式来改善个人计算机或主机计算机与硬件中实现的神经网络之间的数据传输速率。 定义表示输入模式的基本合并向量（U'* N n N）来描述所有向量（U N，N，N，N，N） 代表其导出的输入模式（U'，N“，...，U”n + 6）的组合，通过组合具有固定的“不” 护理价值观。 基本合并向量仅与向量的所有分量一起提供。 然后将人造神经网络（ANN）配置为并行操作的子网络的组合。 为了用足够数量的组件计算距离，原型还包括具有确定值和“无关紧要”条件的组件。 在学习阶段，合并的向量存储为原型。 在识别阶段，当向ANN提供新的基本合并向量时，每个子网络分析其一部分。在计算所有距离之后，它们一次对一个子网进行排序，以获得与每个向量相关联的距离。
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公开(公告)号：US07352918B2
公开(公告)日：2008-04-01
申请号：US10321166
申请日：2002-12-17
IPC分类号： G06K9/32
CPC分类号： G06T3/4046
摘要： An artificial neural network (ANN) based system that is adapted to process an input pattern to generate an output pattern related thereto having a different number of components than the input pattern. The system (26) is comprised of an ANN (27) and a memory (28), such as a DRAM memory, that are serially connected. The input pattern (23) is applied to a processor (22), where it can be processed or not (the most general case), before it is applied to the ANN and stored therein as a prototype (if learned). A category is associated with each stored prototype. The processor computes the coefficients that allow the determination of the estimated values of the output pattern, these coefficients are the components of a so-called intermediate pattern (24). Assuming the ANN has already learned a number of input patterns, when a new input pattern is presented to the ANN in the recognition phase, the category of the closest prototype is output therefrom and is used as a pointer to the memory. In turn, the memory outputs the corresponding intermediate pattern. The input pattern and the intermediate pattern are applied to the processor to construct the output pattern (25) using the coefficients. Typically, the input pattern is a block of pixels in the field of scaling images.
摘要翻译： 一种基于人造神经网络（ANN）的系统，其适于处理输入模式以产生与其相关的输出模式，该输出模式具有与输入模式不同数量的分量。 系统（26）由串联连接的ANN（27）和存储器（28）（诸如DRAM存储器）组成。 将输入模式（23）应用于处理器（22），在处理器（22）被应用于ANN并作为原型存储（如果被学习）之前）处理器（22），其可被处理（最常见的情况））。 类别与每个存储的原型相关联。 处理器计算允许确定输出图案的估计值的系数，这些系数是所谓的中间图案的分量（24）。 假设ANN已经学习了许多输入模式，当在识别阶段向ANN呈现新的输入模式时，最近的原型的类别从其输出并被用作指向存储器的指针。 反过来，存储器输出相应的中间模式。 将输入图案和中间图案应用于处理器，以使用系数构造输出图案（25）。 通常，输入图案是缩放图像领域的像素块。
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7.发明授权Method and circuits for associating a norm to each component of an input pattern presented to a neural network 失效用于将范数与呈现给神经网络的输入模式的每个分量相关联的方法和电路公开(公告)号：US06782373B2
公开(公告)日：2004-08-24
申请号：US09682035
申请日：2001-07-12
IPC分类号： G06N302
CPC分类号： G06K9/6215 , G06K9/6276 , G06N3/063
摘要： The method and circuits of the present invention aim to associate a norm to each component of an input pattern presented to an input space mapping algorithm based artificial neural network (ANN) during the distance evaluation process. The set of norms, referred to as the “component” norms is memorized in specific memorization means in the ANN. In a first embodiment, the ANN is provided with a global memory, common for all the neurons of the ANN, that memorizes all the component norms. For each component of the input pattern, all the neurons perform the elementary (or partial) distance calculation with the corresponding prototype components stored therein during the distance evaluation process using the associated component norm. The distance elementary calculations are then combined using a “distance” norm to determine the final distance between the input pattern and the prototypes stored in the neurons. In another embodiment, the set of component norms is memorized in the neurons themselves in the prototype memorization means, so that the global memory is no longer physically necessary. This implementation allows to significantly optimize the consumed silicon area when the ANN is integrated in a silicon chip.
摘要翻译： 本发明的方法和电路旨在将距离评估过程中给出的输入模式的每个分量与基于输入空间映射算法的人造神经网络（ANN）相关联。 被称为“组件”规范的一套规范被记录在ANN中的具体记忆手段中。 在第一实施例中，ANN被提供有存储ANN的所有神经元的全局存储器，其存储所有的分量规范。 对于输入模式的每个分量，所有神经元使用相关的分量范数在距离评估过程中，使用存储在其中的对应的原型分量执行基本（或部分）距离计算。 然后使用“距离”范数组合距离基本计算，以确定输入模式和存储在神经元中的原型之间的最终距离。 在另一个实施例中，组件规范的集合被存储在原型存储装置中的神经元本身中，使得全局存储器不再是物理上必需的。 当ANN集成在硅芯片中时，该实现允许显着优化消耗的硅面积。
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8.发明授权Method and circuits for performing the quick search of the minimum/maximum value among a set of numbers 失效用于在一组数字中快速搜索最小/最大值的方法和电路公开(公告)号：US06748405B2
公开(公告)日：2004-06-08
申请号：US09754639
申请日：2001-01-04
IPC分类号： G06F700
CPC分类号： G06F7/544 , G06F7/22 , G06F9/30021
摘要： In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=K×n). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a “thermometric” coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.
摘要翻译： 在搜索在q位上编码的p个编码集合中的最小值时，每个数字被分割为以n位编码的K个子值（q> = Kxn）。 因此，参数K为每个子值分配等级，使得形成K个比特片，其中每个切片由相同等级的子值组成。 然后使用“温度测量”编码技术，以m位（m> n）对每个子值进行编码。 然后对编码子值（MSB）的第一切片执行并行搜索以确定该切片的最小子值。 所有与子值相关联的数字大于已评估的最小子值的数字将被取消选择。 评估过程以相同的方式继续，直到最后一个切片（LSB）被处理。 在评估过程结束时，保持选中的数字具有最小值。 响应时间（即处理步骤的数目）现在只取决于数字已被分割的子值的数量K. 该方法也适用于搜索最大值。
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公开(公告)号：US20070150621A1
公开(公告)日：2007-06-28
申请号：US11682547
申请日：2007-03-06
申请人： Kerry Kravec , Ali Saidi , Jan Slyfield , Pascal Tannhof
发明人： Kerry Kravec , Ali Saidi , Jan Slyfield , Pascal Tannhof
IPC分类号： G06F3/00
CPC分类号： G06K9/6202 , G06K9/00986
摘要： A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern has an Opcode that defines what action to take when a particular data in the input data stream either matches or does not match the corresponding data being compared during a clock cycle. Each of the PUs communicate selected information so that PUs may be cascaded to enable longer patterns to be matched or to allow more patterns to be processed in parallel for a particular input data stream.
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10.发明申请Intrusion detection using a network processor and a parallel pattern detection engine 有权使用网络处理器和并行模式检测引擎的入侵检测公开(公告)号：US20050154916A1
公开(公告)日：2005-07-14
申请号：US10756904
申请日：2004-01-14
申请人： Marc Boulanger , Clark Jeffries , C. Kinard , Kerry Kravec , Ravinder Sabhikhi , Ali Saidi , Jan Slyfield , Pascal Tannhof
发明人： Marc Boulanger , Clark Jeffries , C. Kinard , Kerry Kravec , Ravinder Sabhikhi , Ali Saidi , Jan Slyfield , Pascal Tannhof
CPC分类号： H04L63/1416 , H04L63/1441
摘要： An intrusion detection system (IDS) comprises a network processor (NP) coupled to a memory unit for storing programs and data. The NP is also coupled to one or more parallel pattern detection engines (PPDE) which provide high speed parallel detection of patterns in an input data stream. Each PPDE comprises many processing units (PUs) each designed to store intrusion signatures as a sequence of data with selected operation codes. The PUs have configuration registers for selecting modes of pattern recognition. Each PU compares a byte at each clock cycle. If a sequence of bytes from the input pattern match a stored pattern, the identification of the PU detecting the pattern is outputted with any applicable comparison data. By storing intrusion signatures in many parallel PUs, the IDS can process network data at the NP processing speed. PUs may be cascaded to increase intrusion coverage or to detect long intrusion signatures.
摘要翻译： 入侵检测系统（IDS）包括耦合到用于存储程序和数据的存储器单元的网络处理器（NP）。 NP还耦合到一个或多个并行模式检测引擎（PPDE），其提供对输入数据流中的模式的高速并行检测。 每个PPDE包括许多处理单元（PU），每个处理单元被设计为将入侵签名存储为具有所选操作码的数据序列。 PU具有用于选择模式识别模式的配置寄存器。 每个PU在每个时钟周期比较一个字节。 如果来自输入模式的字节序列与存储的模式匹配，则用任何适用的比较数据输出检测模式的PU的识别。 通过在多个并行PU中存储入侵签名，IDS可以以NP处理速度处理网络数据。 PU可以级联以增加入侵覆盖或检测长入侵签名。
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