公开(公告)号：US5768631A

公开(公告)日：1998-06-16

申请号：US533487

申请日：1995-09-25

申请人： Patrick K. Kam ,  Robert J. Devins ,  Stephen Hon ,  Emory D. Keller

发明人： Patrick K. Kam ,  Robert J. Devins ,  Stephen Hon ,  Emory D. Keller

IPC分类号： G06F3/16 ,  G06F13/00

摘要： An audio system is provided for generating audio sound for a host computer. It includes an interface connector for connection with the host computer; an interface controller for communicating with the host computer using the interface connector; a trap adapted to trap audio instruction signals from an application running on the host, such as a game having an audio portion; a trap controller adapted to control the trap; and an audio output. The system operates with an interface communicator which is adapted to respond to a request from the interface controller to read information from the trap and send audio output instruction to the audio output to generate audio sound.

摘要翻译： 提供音频系统以产生用于主计算机的音频声音。 它包括用于与主机连接的接口连接器; 接口控制器，用于使用接口连接器与主机通信; 陷阱，适于从主机上运行的应用捕获音频指令信号，例如具有音频部分的游戏; 适于控制所述陷阱的陷阱控制器; 和音频输出。 该系统与接口通信器一起操作，该接口通信器适于响应来自接口控制器的请求以从陷阱读取信息，并将音频输出指令发送到音频输出以产生音频声音。

公开(公告)号：US5784595A

公开(公告)日：1998-07-21

申请号：US908214

申请日：1997-08-07

申请人： Robert J. Devins ,  Stephen Hon ,  Patrick Kam ,  Emory D. Keller

发明人： Robert J. Devins ,  Stephen Hon ,  Patrick Kam ,  Emory D. Keller

IPC分类号： G06F9/455 ,  G06F13/10 ,  G06F13/28 ,  G06F31/00 ,  G06F13/32

CPC分类号： G06F9/45537 ,  G06F13/105 ,  G06F13/28

摘要： A method and system are disclosed for simulating a direct memory access (DMA) function to access memory in a host computer having a DMA controller for the purpose of enabling the transfer of data between the host memory and a computer accessory data handling device not capable of DMA operation. The accessory data handling device can be operably connected to the host. The address contents of the DMA controller can be read to determine the location in the host memory where data is to be transferred from the host memory to the accessory data handling device or from the accessory data handling device to the host memory. Data is read from the host memory at the address specified in the DMA controller and written to the accessory data handling device or read from the accessory data handling device and written to the host memory at the address specified by the DMA controller, respectively. The host computer is informed that a DMA operation corresponding to the data transfer has been completed when the data transfer required has been completed.

摘要翻译： 公开了一种用于模拟直接存储器访问（DMA）功能以访问具有DMA控制器的主计算机中的存储器的方法和系统，以便能够在主机存储器和不能够执行以下操作的计算机辅助数据处理设备之间传输数据 DMA操作。 附件数据处理装置可以可操作地连接到主机。 可以读取DMA控制器的地址内容，以确定主机存储器中要从主机存储器传输到附件数据处理设备或从附件数据处理设备传输到主机存储器的位置。 数据从DMA控制器中指定的地址从主机存储器读取，并写入附件数据处理设备或从附件数据处理设备读取，并分别以DMA控制器指定的地址写入主机存储器。 当完成数据传输时，主计算机通知对应于数据传输的DMA操作已经完成。

公开(公告)号：US06865502B2

公开(公告)日：2005-03-08

申请号：US09826035

申请日：2001-04-04

申请人： Robert J. Devins ,  Paul J. Ferro ,  Peter D. LaFauci ,  Kenneth A. Mahler ,  David W. Milton

发明人： Robert J. Devins ,  Paul J. Ferro ,  Peter D. LaFauci ,  Kenneth A. Mahler ,  David W. Milton

IPC分类号： G01R31/319 ,  G01R31/14 ,  G06F19/00

CPC分类号： G01R31/318357 ,  G01R31/319 ,  G06F17/5022

摘要： Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

公开(公告)号：US06539522B1

公开(公告)日：2003-03-25

申请号：US09494907

申请日：2000-01-31

申请人： Robert J. Devins ,  Paul G. Ferro ,  Robert D. Herzl ,  Mark E. Kautzman ,  Kenneth A. Mahler ,  David W. Milton

发明人： Robert J. Devins ,  Paul G. Ferro ,  Robert D. Herzl ,  Mark E. Kautzman ,  Kenneth A. Mahler ,  David W. Milton

IPC分类号： G06F1750

CPC分类号： G01R31/318357 ,  G06F17/5022

摘要： A method for developing re-usable software for the efficient verification of system-on-chip (SOC) integrated circuit designs. The verification software is used to generate and apply test cases to stimulate components of a SOC design (“cores”) in simulation; the results are observed and used to de-bug the design. The software is hierarchical, implementing a partition between upper-level test application code which generates test cases and verifies results, and low-level device driver code which interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. Test application and supporting low-level device driver pairs are used and re-used to test their corresponding component cores throughout the SOC development process, by creating higher-level test control programs which control selected combinations of the already-developed test application and device driver programs to test combinations of SOC components. The method provides for the efficient verification of SOC designs and, consequently, a reduced time-to-market for SOC products, because as the verification software is developed and stored, it becomes possible to test increasingly complex core combinations by creating relatively few high-level test programs which re-use already-existing lower-level software. Ultimately, the task of verifying a complex SOC design may be simplified to developing a single chip-specific test program which selects from already-existing test application, device driver and test control programs to perform a realistic test of a chip-specific combination of cores.

摘要翻译： 一种用于开发用于片上系统（SOC）集成电路设计的有效验证的可重用软件的方法。 验证软件用于生成和应用测试用例，以刺激模拟中SOC设计（“核心”）的组件; 观察结果并用于对设计进行设计。 该软件是分级的，实现生成测试用例的上级测试应用程序代码和验证结果之间的分区，以及与正在模拟的内核接口的低级设备驱动程序代码，以应用由上级代码生成的测试用例 在硬件层面的操作。 测试应用程序和支持低级设备驱动程序对被使用并重新用于在SOC开发过程中测试其相应的组件核心，通过创建更高级别的测试控制程序来控制已经开发的测试应用程序和设备驱动程序的选定组合 测试SOC组件组合的程序。 该方法提供SOC设计的有效验证，从而缩短了SOC产品的上市时间，因为随着验证软件的开发和存储，可以通过创建相对较少的高可用性测试来测试日益复杂的核心组合， 重新使用已经存在的低级软件的级别测试程序。 最终，可以简化验证复杂SOC设计的任务，以开发单个芯片特定的测试程序，该测试程序从已经存在的测试应用程序，设备驱动程序和测试控制程序中进行选择，以执行芯片特定的内核组合的现实测试 。

公开(公告)号：US08234624B2

公开(公告)日：2012-07-31

申请号：US11626967

申请日：2007-01-25

申请人： Robert J. Devins ,  Nagashyamala R. Dhanwada

发明人： Robert J. Devins ,  Nagashyamala R. Dhanwada

IPC分类号： G06F9/44

CPC分类号： G06F17/505

摘要： A development system for developing new peripheral software code for new peripheral hardware that will be used in a new integrated system. The development system includes a legacy, or preexisting, integrated system substantially the same as the new integrated system. A model of the new peripheral hardware is made. Each I/O register of the model is mapped into memory-mapped I/O space. Development code corresponding to the new peripheral software code is executed on the preexisting hardware so as to interact with the model via the memory-mapped I/O space. In one embodiment, the model is executed as an embedded model on the preexisting integrated system. In another embodiment, the model is executed as a non-embedded model on a hardware descriptive language simulator.

摘要翻译： 用于开发新外设硬件的新外设软件开发系统，将用于新的集成系统。 开发系统包括与新集成系统基本相同的遗留或预先存在的集成系统。 制作了新的外设硬件的型号。 模型的每个I / O寄存器映射到内存映射的I / O空间。 对应于新的外围设备软件代码的开发代码在预先存在的硬件上执行，以便通过存储器映射的I / O空间与模型进行交互。 在一个实施例中，该模型作为预先存在的集成系统上的嵌入式模型来执行。 在另一个实施例中，该模型作为非嵌入式模型被执行在硬件描述语言模拟器上。

公开(公告)号：US20080184193A1

公开(公告)日：2008-07-31

申请号：US11626967

申请日：2007-01-25

申请人： Robert J. Devins ,  Nagashyamala R. Dhanwada

发明人： Robert J. Devins ,  Nagashyamala R. Dhanwada

IPC分类号： G06F9/44

CPC分类号： G06F17/505

摘要： A development system for developing new peripheral software code for new peripheral hardware that will be used in a new integrated system. The development system includes a legacy, or preexisting, integrated system substantially the same as the new integrated system. A model of the new peripheral hardware is made. Each I/O register of the model is mapped into memory-mapped I/O space. Development code corresponding to the new peripheral software code is executed on the preexisting hardware so as to interact with the model via the memory-mapped I/O space. In one embodiment, the model is executed as an embedded model on the preexisting integrated system. In another embodiment, the model is executed as a non-embedded model on a hardware descriptive language simulator.

摘要翻译： 用于开发新外设硬件的新外设软件开发系统，将用于新的集成系统。 开发系统包括与新集成系统基本相同的遗留或预先存在的集成系统。 制作了新的外设硬件的型号。 模型的每个I / O寄存器映射到内存映射的I / O空间。 对应于新的外围设备软件代码的开发代码在预先存在的硬件上执行，以便通过存储器映射的I / O空间与模型进行交互。 在一个实施例中，该模型作为预先存在的集成系统上的嵌入式模型来执行。 在另一个实施例中，该模型作为非嵌入式模型被执行在硬件描述语言模拟器上。

公开(公告)号：US20080133206A1

公开(公告)日：2008-06-05

申请号：US11969991

申请日：2008-01-07

申请人： Robert J. Devins ,  Robert D. Herzl ,  David W. Milton

发明人： Robert J. Devins ,  Robert D. Herzl ,  David W. Milton

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.

摘要翻译： 提供一种用于验证集成电路设计的系统和方法。 该系统包括：连接到一个或多个I / O核心的I / O控制器，集成电路设计的I / O核心部分; 具有用于选择性地将一个或多个所述I / O核心连接到相应的I / O驱动器模型的开关的外部存储器映射测试装置; 用于在I / O控制器和开关之间传送信号的总线; 以及用于控制开关的测试操作系统。

公开(公告)号：US08140314B2

公开(公告)日：2012-03-20

申请号：US12228587

申请日：2008-08-14

申请人： Robert J. Devins ,  David W. Milton

发明人： Robert J. Devins ,  David W. Milton

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.

摘要翻译： 来自总线功能模型和二进制收敛算法的采样计数反馈是为加速器或硬件辅助模拟器生成最佳采样值。 模拟器包括总线功能模型和驱动程序。 软件可读寄存器维持在总线功能模型上执行交易的模拟器提供的多个样本的计数。 对于每个支持的总线功能模型，维护从总线功能模型检索的样本计数和给定硬件辅助仿真器的最后一个采样值，并应用二进制收敛算法，以根据给予硬件辅助的最后一个采样值来生成采样值 模拟器和给定总线功能模型用于交易的最后一个实际采样值。

公开(公告)号：US07849362B2

公开(公告)日：2010-12-07

申请号：US11275092

申请日：2005-12-09

申请人： Robert J. Devins ,  David W. Milton ,  Pascal A. Nsame

发明人： Robert J. Devins ,  David W. Milton ,  Pascal A. Nsame

IPC分类号： G06F11/00

CPC分类号： G06F11/263 ,  G06F11/261

摘要： A method and system comprises creating a test case that is dependent upon known sequences and executing the test case on an originating processor until it reaches a known point. The method further includes executing the test case on a different processor to perform an action and informing the originating processor that the action was taken. The action is verified as being occurred with the originating processor.

摘要翻译： 一种方法和系统包括创建依赖于已知序列的测试用例，并且在始发处理器上执行测试用例，直到到达已知点。 该方法还包括在不同的处理器上执行测试用例以执行动作，并通知始发处理器已采取动作。 该动作被验证为与始发处理器一起发生。

公开(公告)号：US20080312896A1

公开(公告)日：2008-12-18

申请号：US12228587

申请日：2008-08-14

申请人： Robert J. Devins ,  David W. Milton

发明人： Robert J. Devins ,  David W. Milton

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.