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1.发明授权ADSL front-end in a low voltage process that accommodates large line voltages 有权ADSL前端处于低压工艺，可以容纳大的线路电压公开(公告)号：US06904145B2
公开(公告)日：2005-06-07
申请号：US09957955
申请日：2001-09-21
CPC分类号： H04M1/7385
摘要： The asymmetric digital subscriber line receive channel includes: first and second external resistors 20 and 22 coupled to a telephone line 24 and 26; a coarse programmable gain amplifier CPGA formed in a low voltage process having inputs coupled to the first and second external resistors 20 and 22; and a fine programmable gain amplifier PGA1 coupled to an output of the coarse programmable gain amplifier CPGA, and having a very fine gain trim adjustment to compensate for a mismatch between the external resistors 20 and 22 and the coarse programmable gain amplifier CPGA.
摘要翻译： 非对称数字用户线路接收信道包括：耦合到电话线路24和26的第一和第二外部电阻器20和22; 在低电压工艺中形成的粗略可编程增益放大器CPGA，其具有耦合到第一和第二外部电阻器20和22的输入; 以及耦合到粗略可编程增益放大器CPGA的输出的精细可编程增益放大器PGA1，并且具有非常精细的增益调整以补偿外部电阻20和22与粗略可编程增益放大器CPGA之间的失配。
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公开(公告)号：US08269475B2
公开(公告)日：2012-09-18
申请号：US12372139
申请日：2009-02-17
IPC分类号： G05F1/00
CPC分类号： H03F3/217
摘要： A class DH amplifier is provided. The amplifier is generally comprised of a tracking power supply, a class D amplifier section, and a carrier generator. The tracking power supply receives a supply voltage and an analog input signal, and the tracking power supply provides an input for the carrier generator. Based on its input from the tracking power supply, the carrier generator can output a positive ramp signal and a negative ramp signal to the class D amplifier section. The class D amplifier section can generate an output signal base on the analog input signal and the ramp signals from the carrier generator.
摘要翻译： 提供DH类放大器。 放大器通常由跟踪电源，D类放大器部分和载波发生器组成。 跟踪电源接收电源电压和模拟输入信号，跟踪电源为载波发生器提供输入。 基于跟踪电源的输入，载波发生器可以向D类放大器部分输出正斜坡信号和负斜坡信号。 D类放大器部分可以基于模拟输入信号和来自载波发生器的斜坡信号产生输出信号。
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公开(公告)号：US20100207592A1
公开(公告)日：2010-08-19
申请号：US12372139
申请日：2009-02-17
IPC分类号： G05F1/10
CPC分类号： H03F3/217
摘要： A class DH amplifier is provided. The amplifier is generally comprised of a tracking power supply, a class D amplifier section, and a carrier generator. The tracking power supply receives a supply voltage and an analog input signal, and the tracking power supply provides an input for the carrier generator. Based on its input from the tracking power supply, the carrier generator can output a positive ramp signal and a negative ramp signal to the class D amplifier section. The class D amplifier section can generate an output signal base on the analog input signal and the ramp signals from the carrier generator.
摘要翻译： 提供DH类放大器。 放大器通常由跟踪电源，D类放大器部分和载波发生器组成。 跟踪电源接收电源电压和模拟输入信号，跟踪电源为载波发生器提供输入。 基于跟踪电源的输入，载波发生器可以向D类放大器部分输出正斜坡信号和负斜坡信号。 D类放大器部分可以基于模拟输入信号和来自载波发生器的斜坡信号产生输出信号。
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公开(公告)号：US20110140774A1
公开(公告)日：2011-06-16
申请号：US12639712
申请日：2009-12-16
申请人： Cetin Kaya , Richard K. Hester
发明人： Cetin Kaya , Richard K. Hester
IPC分类号： H03F3/68
CPC分类号： H03F3/2173 , H03F3/3022 , H03F3/45475 , H03F2203/45528 , H03F2203/45712
摘要： One-sided pulse width modulated (PWM) amplifiers are disclosed. An example amplifier includes an integrator to receive first and second analog signals, and to output a first amplified signal and a second amplified signal based on the first and second analog signals, a reference changer coupled to the integrator to determine whether a first amplitude is higher than a second amplitude based on the first and second analog signals, to selectively cause the integrator to apply a first resistance between a reference node and the first amplified signal and apply a second resistance between the reference node and the second amplified signal when the first amplitude is higher than the second amplitude, and to selectively cause the integrator to apply the second resistance between the reference node and the first amplified signal and apply the first resistance between the reference node and the second amplified signal when the second amplitude is higher than the first amplitude, and first and second comparators coupled to the integrator to receive the first and second amplified signals, to compare the first and second amplified signals to a reference signal, and to output first and second pulse width modulated signals having respective first and second pulse widths based on the comparisons between the first and second amplified signals and the reference signal.
摘要翻译： 公开了单侧脉宽调制（PWM）放大器。 示例放大器包括用于接收第一和第二模拟信号的积分器，并且基于第一和第二模拟信号输出第一放大信号和第二放大信号;耦合到积分器的参考变换器，以确定第一幅度是否更高 基于第一和第二模拟信号的第二幅度，选择性地使积分器在参考节点和第一放大信号之间施加第一电阻，并且当第一幅度在参考节点和第二放大信号之间施加第二电阻时 高于第二幅度，并且选择性地使积分器在参考节点和第一放大信号之间施加第二电阻，并且当第二幅度高于第一幅度时，在参考节点和第二放大信号之间施加第一电阻 幅度以及耦合到积分器的第一和第二比较器以接收第一比较器 和第二放大信号，以将第一和第二放大信号与参考信号进行比较，并且基于第一和第二放大信号与参考信号之间的比较，输出具有各自的第一和第二脉冲宽度的第一和第二脉冲宽度调制信号 。
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公开(公告)号：US4903022A
公开(公告)日：1990-02-20
申请号：US130819
申请日：1987-12-09
申请人： Richard K. Hester , Nuboru Shiwaku
发明人： Richard K. Hester , Nuboru Shiwaku
IPC分类号： G06F3/05
CPC分类号： G06F3/05
摘要： An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital data from the signal processor to the system, and converts it to analog as the output of the system. The digital signal processor determines whether the sampling rate of the D-to-A and A-to-D converters is correct for the rate at which the data is being received by the respective converters. If not, the DSP sends a number of master clock cycles to the system which then retards or advances the sampling rate of the converter by that number of clock cycles.
摘要翻译： 模拟接口系统与数字信号处理器接口。 系统接收模拟信号，对这些信号进行数字化，并在完成转换后将其传输到信号处理器。 系统将数字数据从信号处理器传输到系统，并将其转换为模拟信号作为系统的输出。 数字信号处理器确定D-A和A-D转换器的采样率对于各个转换器正在接收数据的速率是否正确。 如果没有，则DSP向系统发送多个主时钟周期，然后将该转换器的采样速率延迟或提前若干个时钟周期。
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6.发明授权Switching method to improve the efficiency of switched-mode power converters employing a bridge topology 有权采用桥接拓扑的开关式功率转换器的效率提高的切换方法公开(公告)号：US08415937B2
公开(公告)日：2013-04-09
申请号：US12872896
申请日：2010-08-31
申请人： Richard K. Hester
发明人： Richard K. Hester
CPC分类号： H02M3/1582 , Y10T307/50
摘要： Traditionally, buck-boost switching regulators with bridge topologies have been avoided due to their inability to seamlessly transition between buck mode and boost mode. Here, however, a buck-boost switching regulator with a bridge topology has been provided, which has an improved controller. Namely, a processor (such as a digital signals processor or DSP) provides digital control for the bridge to enable it so substantially seamlessly transition between buck mode and boost mode.
摘要翻译： 传统上，由于它们无法在降压模式和升压模式之间无缝转换，因此避免了具有桥接拓扑的降压 - 升压开关稳压器。 然而，这里提供了具有桥接拓扑的降压 - 升压开关稳压器，其具有改进的控制器。 也就是说，处理器（例如数字信号处理器或DSP）为桥提供数字控制，使得它能够在降压模式和升压模式之间基本上无缝地转换。
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公开(公告)号：US5038143A
公开(公告)日：1991-08-06
申请号：US350497
申请日：1989-05-11
申请人： Richard K. Hester
发明人： Richard K. Hester
IPC分类号： G06F3/05
CPC分类号： G06F3/05
摘要： An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital data from the signal processor to the system, and converts it to analog as the output of the system. The A-to-D and D-to-A conversion rates are selected by the system control, responsive to data received from the signal processor.
摘要翻译： 模拟接口系统与数字信号处理器接口。 系统接收模拟信号，对这些信号进行数字化，并在完成转换后将其传输到信号处理器。 系统将数字数据从信号处理器传输到系统，并将其转换为模拟信号作为系统的输出。 响应于从信号处理器接收的数据，系统控制器选择A到D和D到A的转换速率。
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公开(公告)号：US4638451A
公开(公告)日：1987-01-20
申请号：US491140
申请日：1983-05-03
申请人： Richard K. Hester , Khen-Sang Tan
发明人： Richard K. Hester , Khen-Sang Tan
摘要： A microprocessor system includes a CPU device with on-chip or off-chip memory, and data and control busses for accessing memory and/or peripherals. The peripheral circuitry includes one or more channels for input and/or output of data, wherein various characteristics of the treatment of data in the channel are controlled by the program being executed in the CPU. In one embodiment analog input and output channels are included, and the A-to-D or D-to-A conversion rates are selected by executing a data output instruction by the CPU. The cut-off points of the filters are likewise selected. The A-to-D converter loads a first-in first-out memory which is read by the CPU in burst mode when filled. Likewise, the CPU loads digital data to a first-in first-out memory in the output channel, and then the D-to-A converts at its selected rate.
摘要翻译： 微处理器系统包括具有片上或片外存储器的CPU装置以及用于访问存储器和/或外围设备的数据和控制总线。 外围电路包括用于输入和/或输出数据的一个或多个通道，其中通道中数据处理的各种特性由在CPU中执行的程序控制。 在一个实施例中，包括模拟输入和输出通道，并且通过执行CPU的数据输出指令来选择A到D或D到A的转换速率。 同样选择过滤器的截止点。 A到D转换器加载先进先出的存储器，当CPU被填充时，它以突发模式读取。 同样，CPU将数字数据加载到输出通道中的先进先出存储器，然后D到A以其选定的速率转换。
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公开(公告)号：US06925171B2
公开(公告)日：2005-08-02
申请号：US10159524
申请日：2002-05-30
申请人： Minsheng Wang , Richard K. Hester
发明人： Minsheng Wang , Richard K. Hester
CPC分类号： H04M3/005
摘要： A codifier/decodifier (CODEC) filter circuit (250) connected in a subscriber line interface circuit (202) includes a transmit section (264, 262, 260) for converting differential voltage audio transmit signals representing voice transmissions from the subscriber instrument (202) into encoded digital data for transmission to the digital switching network. A receive section (254, 252) coupled between the digital switching network and subscriber instrument (202) within CODEC (250) for converting encoded digital data representing voice signals switched through the digital switching network to differential voltage audio receive signals for transmission to the subscriber instrument (202). The subscriber loop and subscriber instrument (202) reflect the digital voltage audio signals to the transmit section (264, 262, 260). An impedance section (258, 256) within CODEC (250) connects between the transmit section (264, 262, 260) and the receive section (254, 252) and is disposed to provide an audio band feedback signal between the transmit section (264, 262, 260) and the receive section (254, 252) for synthesizing a source impedance for the subscriber line that matches the subscriber loop impedance. Impedance section (258, 256) includes an analog impedance scaling network (246) coupled between the transmit section (264, 262, 260) and receive section (254, 252). The impedance section (258, 256) also includes a programmable digital filter (258) coupled to the transmit section (264, 262, 260) having a transfer function equal to: (R2T)(1+z−1)/(R1(T+2C2R2)(1+(T−2R2C2)/(T+2R2C2)z−1) where R2 is the second subscriber loop impedance, C2 is the subscriber loop capacitance, R1 is the first subscriber loop impedance, T is the sampling rate of the analog-to-digital converter and z is the frequency of the signal. Furthermore, a summer circuit (256) provides feedback between the programmable digital filter (258) and the receive section (254, 252) by summing the single-ended audio receive signals from the digital switching network with the audio band feedback signal output by the programmable digital filter (258).
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公开(公告)号：US5235335A
公开(公告)日：1993-08-10
申请号：US892447
申请日：1992-06-02
申请人： Richard K. Hester , Khen-Sang Tan , Michiel de Wit
发明人： Richard K. Hester , Khen-Sang Tan , Michiel de Wit
CPC分类号： H03M1/1033 , H03M1/804
摘要： A capacitor array circuit is disclosed herein. A main capacitor array includes at least a most significant array portion 12 and a least significant array portion 14. A coupling capacitor C.sub.C is formed between the two portions of the array. Typically, one plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the least significant array portion 14 and a second plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the most significant array portion 12. A variable calibration capacitor C.sub.CAL is also provided. In a preferred embodiment, the variable calibration capacitor C.sub.CAL is coupled between the coupling capacitor C.sub.C and an AC ground node. In alternate embodiment, the variable calibration capacitor C.sub.CAL is coupled in parallel with the coupling capacitor C.sub.C. In the preferred embodiment, the variable calibration capacitor C.sub.CAL comprises array 26 of calibration capacitors 28a-28n, each associated with a switch element 30a- 30n. The array 26 may be a binary weighted array.
摘要翻译： 本文公开了一种电容器阵列电路。 主电容器阵列至少包括最有效的阵列部分12和最不重要的阵列部分14.耦合电容器CC形成在阵列的两个部分之间。 通常，耦合电容器CC的一个板耦合到最不重要的阵列部分14中的每个电容器的顶板，并且耦合电容器CC的第二板最多地耦合到每个电容器的顶板 还提供可变校准电容器CCAL。 在优选实施例中，可变校准电容器CCAL耦合在耦合电容器CC和AC接地节点之间。 在替代实施例中，可变校准电容器CCAL与耦合电容器CC并联耦合。 在优选实施例中，可变校准电容器CCAL包括校准电容器28a-28n的阵列26，每个与开关元件30a-30n相关联。 阵列26可以是二进制加权阵列。
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