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    Infrastructure Support for Accelerated Processing Device Memory Paging Without Operating System Integration
    1.
    发明申请
    Infrastructure Support for Accelerated Processing Device Memory Paging Without Operating System Integration 有权
    基础设施支持加速处理设备内存寻呼，无需操作系统集成

    公开(公告)号：US20130159664A1

    公开(公告)日：2013-06-20

    申请号：US13325282

    申请日：2011-12-14

    申请人： Paul BLINZER ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

    发明人： Paul BLINZER ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1009 ,  G06F9/3004 ,  G06F9/3881 ,  G06F12/1081 ,  G06F2009/3883 ,  G06F2212/683

    摘要： In a CPU of the combined CPU/APD architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to an APD, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.

    摘要翻译： 在组合的CPU / APD架构系统的CPU中，CPU具有多个CPU内核，每个核具有用于接收物理页表/页目录基地址的第一机器特定寄存器，用于接收物理地址指向 到由通信地耦合到APD的IOMMUv2控制的位置，以及当被执行时导致向包含在第二机器特定寄存器中的物理地址发出写入通知的微代码; 在CPU核心的第一机器特定寄存器中接收物理页表/页目录基地址，在CPU核心的第二机器特定寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制 已经更新了CPU核心的寄存器，并且响应于控制寄存器被更新的确定，执行CPU核心中的微代码，使得向第二机器特定寄存器中包含的物理地址发出写入通知，其中， 物理地址能够接收影响IOMMUv2页表无效的写入。

    GRAPHICS COMPUTE PROCESS SCHEDULING
    2.
    发明申请
    GRAPHICS COMPUTE PROCESS SCHEDULING 有权
    图形计算过程调度

    公开(公告)号：US20120147021A1

    公开(公告)日：2012-06-14

    申请号：US13289260

    申请日：2011-11-04

    申请人： Jeffrey Gongxian CHENG ,  Paul BLINZER ,  Mark HUMMEL ,  Leendert Peter VAN DOORN

    发明人： Jeffrey Gongxian CHENG ,  Paul BLINZER ,  Mark HUMMEL ,  Leendert Peter VAN DOORN

    IPC分类号： G06T1/00

    CPC分类号： G06F9/545 ,  G06F2209/509

    摘要： A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.

    摘要翻译： 公开了一种方法，系统和计算机程序产品，用于提供对用户模式应用的加速处理设备计算资源的改进访问。 所公开的功能允许用户模式应用程序向加速处理设备提供命令，而不需要内核模式转换以便访问统一的环形缓冲区。 相反，应用程序各自提供有自己的缓冲区，加速处理设备硬件可以访问进程命令。 通过完整的操作系统支持，用户模式应用程序能够以与CPU相同的方式利用加速处理设备。