公开(公告)号：US08797332B2

公开(公告)日：2014-08-05

申请号：US13325824

申请日：2011-12-14

申请人： Paul Blinzer ,  Leendert Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Woller ,  Arshad Rahman

发明人： Paul Blinzer ,  Leendert Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Woller ,  Arshad Rahman

IPC分类号： G06F15/00 ,  G06T1/00 ,  G06F15/16 ,  G06T1/60

CPC分类号： G06T1/20 ,  G06F9/30003

摘要： Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.

摘要翻译： 提供了作为组合的CPU / APD架构系统的一个方面的方法和装置，用于发现和报告与有效地调度和分发计算任务到组合的CPU / APD架构的各种计算资源相关的设备和系统拓扑的属性 系统。 组合的CPU / APD架构将CPU和APD统一在灵活的计算环境中。 在一些实施例中，组合的CPU / APD架构能力在单个集成电路中实现，其单元可以包括一个或多个CPU核心和一个或多个APD核心。 组合的CPU / APD架构创建了可以构建现有和新的编程框架，语言和工具的基础。

公开(公告)号：US20120001905A1

公开(公告)日：2012-01-05

申请号：US13173958

申请日：2011-06-30

申请人： Joseph ANDONIEH ,  Arshad Rahman

发明人： Joseph ANDONIEH ,  Arshad Rahman

IPC分类号： G06F15/16

CPC分类号： G06T1/20

摘要： A computer based rendering system is provided. The computer based rendering system includes an abstraction mechanism to provide configuring instructions to two or more processors, the configuring instructions being operative to facilitate scene rendering. The configuring provides processor setup instructions to at least one driver. Each of the two or more processors renders a respective portion of the scene independent of the other of the processors.

摘要翻译： 提供基于计算机的渲染系统。 基于计算机的呈现系统包括一个抽象机制，用于向两个或多个处理器提供配置指令，该配置指令可操作以便于场景呈现。 该配置向至少一个驱动程序提供处理器设置指令。 两个或更多个处理器中的每一个呈现与独立于处理器中的另一个的场景的相应部分。

公开(公告)号：US08578129B2

公开(公告)日：2013-11-05

申请号：US13325282

申请日：2011-12-14

申请人： Paul Blinzer ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

发明人： Paul Blinzer ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

IPC分类号： G06F12/00

CPC分类号： G06F12/1009 ,  G06F9/3004 ,  G06F9/3881 ,  G06F12/1081 ,  G06F2009/3883 ,  G06F2212/683

摘要： In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.

摘要翻译： 在CPU中，具有多个CPU核心的CPU，每个核心具有第一机器特定寄存器，第二机器特定寄存器和微代码，当被执行时，将对包含在第二机器特定寄存器中的物理地址发出写入通知; 在CPU核心的第一机器特定寄存器中接收物理页表/页目录基地址，在CPU核心的第二机器特定寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制 已经更新了CPU核心的寄存器，并且响应于控制寄存器被更新的确定，执行CPU核心中的微代码，使得向第二机器特定寄存器中包含的物理地址发出写入通知，其中， 物理地址能够接收影响IOMMUv2页表无效的写入。

公开(公告)号：US20120162234A1

公开(公告)日：2012-06-28

申请号：US13325824

申请日：2011-12-14

申请人： Paul Blinzer ,  Leendert Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Woller ,  Arshad Rahman

发明人： Paul Blinzer ,  Leendert Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Woller ,  Arshad Rahman

IPC分类号： G06T1/20 ,  G06T1/60

CPC分类号： G06T1/20 ,  G06F9/30003

摘要： Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.

摘要翻译： 提供了作为组合的CPU / APD架构系统的一个方面的方法和装置，用于发现和报告与有效地调度和分发计算任务到组合的CPU / APD架构的各种计算资源相关的设备和系统拓扑的属性 系统。 组合的CPU / APD架构将CPU和APD统一在灵活的计算环境中。 在一些实施例中，组合的CPU / APD架构能力在单个集成电路中实现，其单元可以包括一个或多个CPU核心和一个或多个APD核心。 组合的CPU / APD架构创建了可以构建现有和新的编程框架，语言和工具的基础。

公开(公告)号：US20130159664A1

公开(公告)日：2013-06-20

申请号：US13325282

申请日：2011-12-14

申请人： Paul BLINZER ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

发明人： Paul BLINZER ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F9/3004 ,  G06F9/3881 ,  G06F12/1081 ,  G06F2009/3883 ,  G06F2212/683

摘要： In a CPU of the combined CPU/APD architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to an APD, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.

摘要翻译： 在组合的CPU / APD架构系统的CPU中，CPU具有多个CPU内核，每个核具有用于接收物理页表/页目录基地址的第一机器特定寄存器，用于接收物理地址指向 到由通信地耦合到APD的IOMMUv2控制的位置，以及当被执行时导致向包含在第二机器特定寄存器中的物理地址发出写入通知的微代码; 在CPU核心的第一机器特定寄存器中接收物理页表/页目录基地址，在CPU核心的第二机器特定寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制 已经更新了CPU核心的寄存器，并且响应于控制寄存器被更新的确定，执行CPU核心中的微代码，使得向第二机器特定寄存器中包含的物理地址发出写入通知，其中， 物理地址能够接收影响IOMMUv2页表无效的写入。

公开(公告)号：US20120001925A1

公开(公告)日：2012-01-05

申请号：US13173995

申请日：2011-06-30

申请人： Joseph ANDONIEH ,  Arshad RAHMAN

发明人： Joseph ANDONIEH ,  Arshad RAHMAN

IPC分类号： G06F15/16

CPC分类号： G06F9/5083 ,  G06F15/16 ,  G06F2209/508 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005

摘要： A method for rendering a scene across N number of processors is provided. The method includes evaluating performance statistics for each of the processors and establishing load rendering boundaries for each of the processors, the boundaries defining a respective portion of the scene. The method also includes dynamically adjusting the boundaries based upon the establishing and the evaluating.

摘要翻译： 提供了一种用于在N个处理器上渲染场景的方法。 该方法包括评估每个处理器的性能统计信息，并为每个处理器建立负载渲染边界，边界限定场景的相应部分。 该方法还包括基于建立和评估来动态调整边界。

公开(公告)号：US5901310A

公开(公告)日：1999-05-04

申请号：US871781

申请日：1997-09-11

申请人： Arshad Rahman ,  Vladimir Velenta ,  Anthony Scarpino

发明人： Arshad Rahman ,  Vladimir Velenta ,  Anthony Scarpino

IPC分类号： G06F9/445 ,  H03M7/30 ,  H03M7/46 ,  G06F9/00

CPC分类号： G06F9/4401 ,  H03M7/30 ,  H03M7/46

摘要： Initializing and configuring computer hardware with firmware stored in compressed form in nonvolatile semiconductor memory. Upon startup of the computer hardware, decompression software decompress the firmware, which is then stored in another memory. The computer hardware may be an adapter board (e.g., a graphics board connected to PCI bus), the nonvolatile semiconductor memory may be physically located on the adapter board, and the firmware may be firmware for initializing and configuring the adapter board. The decompression software may be stored in the same nonvolatile semiconductor memory as the firmware, and may be written in a machine-independent language (e.g., a Forth-based language). The compression technique used may include both run-length encoding and pattern compression, and may operate at the bit level.

摘要翻译： 使用非易失性半导体存储器中以压缩形式存储的固件来初始化和配置计算机硬件。 在计算机硬件启动时，解压缩软件解压缩固件，然后存储在另一个存储器中。 计算机硬件可以是适配器板（例如，连接到PCI总线的图形板），非易失性半导体存储器可以物理地位于适配器板上，固件可以是用于初始化和配置适配器板的固件。 解压缩软件可以存储在与固件相同的非易失性半导体存储器中，并且可以以与机器无关的语言（例如，基于Forth的语言）来编写。 所使用的压缩技术可以包括游程长度编码和模式压缩，并且可以在比特级操作。

公开(公告)号：US08675002B1

公开(公告)日：2014-03-18

申请号：US12797033

申请日：2010-06-09

申请人： Joseph Andonieh ,  Arshad Rahman

发明人： Joseph Andonieh ,  Arshad Rahman

IPC分类号： G06T1/00 ,  G06T15/00 ,  G06F15/80 ,  G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06K9/54 ,  G06K9/60

CPC分类号： G06F15/167 ,  G06F9/30072 ,  G06F15/00 ,  G06K9/54 ,  G06K9/60 ,  G06T1/60 ,  G06T15/005

摘要： A method for providing two or more processors access to a single command buffer is provided. The method includes receiving instructions in the command buffer from a central processor, at least one of the instructions being designated for a particular one of the two or more processors. The method also includes sending the at least one instruction to only the particular processor.

摘要翻译： 提供了一种用于提供两个或多个处理器访问单个命令缓冲器的方法。 该方法包括从中央处理器在命令缓冲器中接收指令，为两个或多个处理器中的特定一个处理器指定至少一个指令。 该方法还包括仅向特定处理器发送至少一条指令。