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    ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS
    8.
    发明申请
    ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS 失效
    高速总线上的错误纠正代码保护的静态位通信

    公开(公告)号：US20120272119A1

    公开(公告)日：2012-10-25

    申请号：US13535574

    申请日：2012-06-28

    申请人： Peter Buchmann ,  Kevin C. Gower ,  Robert J. Reese ,  Martin L. Schmatz ,  Michael R. Trombley

    发明人： Peter Buchmann ,  Kevin C. Gower ,  Robert J. Reese ,  Martin L. Schmatz ,  Michael R. Trombley

    IPC分类号： H03M13/05 ,  G06F11/10 ,  H03M13/29

    CPC分类号： H03M13/13 ,  G06F11/10

    摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.

    摘要翻译： 提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。 通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。 通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

    Cascade interconnect memory system with enhanced reliability
    9.
    发明授权
    Cascade interconnect memory system with enhanced reliability 有权
    级联互连存储器系统具有增强的可靠性

    公开(公告)号：US08245105B2

    公开(公告)日：2012-08-14

    申请号：US12166235

    申请日：2008-07-01

    申请人： Timothy J. Dell ,  Kevin C. Gower ,  Warren E. Maule ,  Michael R. Trombley

    发明人： Timothy J. Dell ,  Kevin C. Gower ,  Warren E. Maule ,  Michael R. Trombley

    IPC分类号： H03M13/00

    CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/0781 ,  G06F11/1004 ,  G11C5/04 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/0411

    摘要： A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device.

    摘要翻译： 一种用于提供具有增强的可靠性的级联互连存储器系统的集线器设备，存储器系统和方法。 集线器设备包括与高速总线的接口，用于与存储器控制器进行通信。 存储器控制器和集线器设备包括在级联互连存储器系统中，并且高速总线包括位通道和一个或多个时钟通道。 集线器设备还包括与存储器控制器通信并可由服务接口读取的双向故障信号线。 集线器设备还包括用于存储关于在集线器设备处检测到的故障的信息的故障隔离寄存器（FIR），该信息包括检测到的故障的严重性级别。 此外，集线器设备包括用于响应在集线器设备处检测到的故障的错误恢复逻辑。

    PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY
    10.
    发明申请
    PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY 有权
    在具有INDETERMINATE读取数据延迟的存储器系统中提供帧起始指示

    公开(公告)号：US20120151171A1

    公开(公告)日：2012-06-14

    申请号：US13397819

    申请日：2012-02-16

    申请人： Paul W. Coteus ,  Kevin C. Gower ,  Warren E. Maule ,  Robert B. Tremaine

    发明人： Paul W. Coteus ,  Kevin C. Gower ,  Warren E. Maule ,  Robert B. Tremaine

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1657 ,  G06F13/1673

    摘要： A memory system, having indeterminate read data latency, that includes a memory controller and one or more hub devices. The memory controller is configured for receiving data transfers via an upstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting a frame start indicator. The data frame includes an identification tag that is utilized by the memory controller to associate the data frame with a corresponding read instruction issued by the memory controller. The one or more hub devices are in communication with the memory controller in a cascade interconnect manner via the upstream channel and a downstream channel. Each hub device is configured for receiving the data transfers via the upstream channel or the downstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting the frame start indicator.

    摘要翻译： 具有不确定的读取数据延迟的存储器系统，其包括存储器控制器和一个或多个集线器设备。 存储器控制器被配置为经由上游信道接收数据传输，并且通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。 数据帧包括由存储器控制器用于将数据帧与由存储器控制器发出的相应读取指令相关联的识别标签。 一个或多个集线器设备经由上游信道和下游信道以级联互连方式与存储器控制器通信。 每个集线器设备被配置用于经由上游信道或下游信道接收数据传输，并且用于通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。