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1.发明授权公开(公告)号：US08149979B2
公开(公告)日：2012-04-03
申请号：US12547342
申请日：2009-08-25
申请人： Peter Buchmann , Martin Leo Schmatz
发明人： Peter Buchmann , Martin Leo Schmatz
IPC分类号： H04L7/00
CPC分类号： G06F13/4291 , H04L7/005 , H04L7/0083
摘要： A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.
摘要翻译： 用于串行链路端口的接收器，其通过连接到转发的时钟信号通道的时钟数据恢复环路来增强。 接收机包括由相位位置逻辑控制的相位插值装置，它通过数字低通滤波器从时钟数据恢复环路的本地相位更新信号中获取其更新信号。 接收机还提供全局相位更新源选择逻辑，以控制哪个时钟数据恢复环路正在分发相位更新信息，哪个时钟数据恢复环路正在接收基于时钟分析块的相位更新信息。
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2.发明授权Pseudo-random bit sequence (PRBS) synchronization for interconnects with dual-tap scrambling devices and methods 失效具有双抽头加扰设备和方法的互连的伪随机比特序列（PRBS）同步公开(公告)号：US07492807B1
公开(公告)日：2009-02-17
申请号：US12098878
申请日：2008-04-07
申请人： Peter Buchmann , Martin Leo Schmatz
发明人： Peter Buchmann , Martin Leo Schmatz
IPC分类号： H04B1/00
CPC分类号： G06F13/4234
摘要： A method for synchronizing interconnects in a link system according to various embodiments can include receiving input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scrambling the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmitting the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler; synchronizing the at least one pseudo-random bit sequence scrambler to the at least one pseudo-random bit sequence descrambler; using an edge detection or transition detection device for synchronization of the descrambler to the scrambler; and de-scrambling the transmitted scrambled data at the receive side resulting in the input data.
摘要翻译： 根据各种实施例的用于在链路系统中同步互连的方法可以包括在发送侧接收输入数据，所述发送侧包括至少一个伪随机比特序列加扰器; 经由具有双抽头序列的伪随机比特加扰器在发送侧加扰输入数据，导致加扰数据; 通过经由互连所述多个通道的总线将具有多个通道所有通道的双抽头序列的加扰数据发送到接收侧，所述接收侧包括至少一个伪随机位序列解扰器; 将所述至少一个伪随机比特序列加扰器同步至所述至少一个伪随机比特序列解扰器; 使用边缘检测或转换检测装置来将解扰器同步到扰频器; 并且在接收侧对发送的加扰数据进行去加扰，得到输入数据。
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3.发明申请公开(公告)号：US20070033466A1
公开(公告)日：2007-02-08
申请号：US11484406
申请日：2006-07-11
申请人： Peter Buchmann , Martin Schmatz
发明人： Peter Buchmann , Martin Schmatz
IPC分类号： G01R31/28
CPC分类号： G06F13/4291 , H04L7/005 , H04L7/0083
摘要： A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.
摘要翻译： 用于串行链路端口的接收器，其通过连接到转发的时钟信号通道的时钟数据恢复环路来增强。 接收机包括由相位位置逻辑控制的相位插值装置，它通过数字低通滤波器从时钟数据恢复环路的本地相位更新信号中获取其更新信号。 接收机还提供全局相位更新源选择逻辑，以控制哪个时钟数据恢复循环正在分发相位更新信息，以及哪个时钟数据恢复循环正在接收基于时钟分析块的相位更新信息。
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公开(公告)号：US06768716B1
公开(公告)日：2004-07-27
申请号：US09551049
申请日：2000-04-18
申请人： François G. Abel , Peter Buchmann , Antonius Engbersen , Andreas Herkersdorf , Ronald P. Luijten , David J. Webb
发明人： François G. Abel , Peter Buchmann , Antonius Engbersen , Andreas Herkersdorf , Ronald P. Luijten , David J. Webb
IPC分类号： H04J304
摘要： A real-time load-balancing system for distributing a sequence of incoming data packets emanating from a high speed communication line to a plurality of processing means, each operating at a capacity that is lower than the capacity of the high speed communication line; the system according to the invention comprises: a parser capable of extracting a configurable set of classifier bits from the incoming packets for feeding into a compression means; the compression means is capable of reducing a bit pattern of length K to a bit pattern having a length L which is a fraction of K; a pipeline block for delaying incoming packets until a load balancing decision is found, and an inverse demultiplexer for receiving a port identifier output from said compression means as selector and for directing pipelined packets to the appropriate output port.
摘要翻译： 一种用于将从高速通信线路发出的输入数据分组序列分发到多个处理装置的实时负载平衡系统，每个处理装置以低于高速通信线路的容量的容量运行; 根据本发明的系统包括：解析器，其能够从所述输入分组提取可配置的分类器比特集合，以馈送到压缩装置; 压缩装置能够将长度K的位模式减小为长度L为K的一部分的位图案; 用于延迟输入分组直到发现负载平衡决定的流水线块;以及反向解复用器，用于接收从所述压缩装置输出的端口标识符作为选择器，并将流水线分组引导到适当的输出端口。
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5.发明授权Error correcting code protected quasi-static bit communication on a high-speed bus 失效在高速总线上纠错代码保护的准静态位通信公开(公告)号：US08234540B2
公开(公告)日：2012-07-31
申请号：US12165788
申请日：2008-07-01
IPC分类号： H03M13/00
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译： 提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。 通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。 通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。
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6.发明申请公开(公告)号：US20100061497A1
公开(公告)日：2010-03-11
申请号：US12547342
申请日：2009-08-25
申请人： Peter Buchmann , Martin Leo Schmatz
发明人： Peter Buchmann , Martin Leo Schmatz
IPC分类号： H04L7/00
CPC分类号： G06F13/4291 , H04L7/005 , H04L7/0083
摘要： A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.
摘要翻译： 用于串行链路端口的接收器，其通过连接到转发的时钟信号通道的时钟数据恢复环路来增强。 接收机包括由相位位置逻辑控制的相位插值装置，它通过数字低通滤波器从时钟数据恢复环路的本地相位更新信号中获取其更新信号。 接收机还提供全局相位更新源选择逻辑，以控制哪个时钟数据恢复环路正在分发相位更新信息，哪个时钟数据恢复环路正在接收基于时钟分析块的相位更新信息。
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7.发明申请ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS 失效高速总线上的错误纠正代码保护的静态位通信公开(公告)号：US20100005365A1
公开(公告)日：2010-01-07
申请号：US12165788
申请日：2008-07-01
IPC分类号： H03M13/09
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译： 提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。 通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。 通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。
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公开(公告)号：US5287001A
公开(公告)日：1994-02-15
申请号：US874246
申请日：1992-04-24
申请人： Peter Buchmann , Peter Unger , Peter Vettiger , Otto Voegeli
发明人： Peter Buchmann , Peter Unger , Peter Vettiger , Otto Voegeli
IPC分类号： G12B15/06 , H01L23/34 , H01L23/433 , H01L31/024 , H01L33/48 , H01L33/64 , H01S5/024 , H01L23/02
CPC分类号： H01L31/024 , H01L23/433 , H01L24/72 , H01L33/483 , H01L33/642 , H01L2224/16 , H01L2224/16225 , H01L2224/48091 , H01L2224/48137 , H01L2224/4823 , H01L2224/48471 , H01L2224/73251 , H01L2224/73253 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/10329 , H01L2924/10336 , H01L2924/12042 , H01L2924/1306 , H01L2924/13063 , H01L2924/13091 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/19041 , H01L2924/3025 , H01S5/0071 , H01S5/02248 , H01S5/02264 , H01S5/02469 , H01S5/02476
摘要： Cooling structure for direct heat transfer between an active layer of a chip in which electric elements are formed and a heat sink are disclosed. The inventive cooling structure consists of a current/voltage supply level, with metal structures and insulation spacers and/or layers, partly covered by an insulation layer and followed by a heat transfer structure. A heat transfer bridge is in thermal connection with the heat transfer structure that provides for heat flux between the inventive cooling structure and the heat sink. The inventive cooling structure of this invention can be used with semiconductor devices and/or with opto-electronic devices.
摘要翻译： 公开了在其中形成电气元件的芯片的有源层和散热器之间进行直接传热的冷却结构。 本发明的冷却结构包括电流/电压供应水平，其中金属结构和绝缘间隔物和/或层，部分被绝缘层覆盖并且随后是传热结构。 传热桥与传热结构热连接，该传热结构在本发明的冷却结构和散热器之间提供热通量。 本发明的本发明的冷却结构可以与半导体器件和/或光电器件一起使用。
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公开(公告)号：US08645620B2
公开(公告)日：2014-02-04
申请号：US12143889
申请日：2008-06-23
IPC分类号： G06F12/00
CPC分类号： G06F12/02 , G06F12/0223 , G11C15/00
摘要： An interfacing apparatus and related method is provided for configuring to couple a plurality of memory devices being addressable by means of an address space to a processing unit. In one embodiment, the apparatus comprises a first memory access unit being adapted for receiving a memory address from said processing unit and for accessing said memory devices accordingly based on the address provided. It also comprises a second memory access unit being adapted for receiving content data from the processing unit and for controlling a search or update function accordingly for the received content data in one or more of the memory devices. In addition, an allocation unit is also provided for allocating a first part of the address space of the memory devices to said first memory access unit and allocating a second part of the address space of said memory devices to the second memory access unit, each of the memory access units being assigned to corresponding memory devices of the plurality of memory devices.
摘要翻译： 提供了一种接口装置和相关方法，用于将通过地址空间寻址的多个存储器件耦合到处理单元。 在一个实施例中，该装置包括第一存储器存取单元，其适于从所述处理单元接收存储器地址，并根据所提供的地址相应地访问所述存储器件。 它还包括第二存储器存取单元，其适于从处理单元接收内容数据，并用于相应地控制一个或多个存储器件中的所接收的内容数据的搜索或更新功能。 此外，还提供分配单元，用于将存储器件的地址空间的第一部分分配给所述第一存储器存取单元，并将所述存储器件的地址空间的第二部分分配给第二存储器存取单元， 所述存储器访问单元被分配给所述多个存储器件的相应的存储器件。
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10.发明授权公开(公告)号：US07684534B2
公开(公告)日：2010-03-23
申请号：US11484406
申请日：2006-07-11
申请人： Peter Buchmann , Martin Leo Schmatz
发明人： Peter Buchmann , Martin Leo Schmatz
IPC分类号： H03D3/24
CPC分类号： G06F13/4291 , H04L7/005 , H04L7/0083
摘要： A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.
摘要翻译： 用于串行链路端口的接收器，其通过连接到转发的时钟信号通道的时钟数据恢复环路来增强。 接收机包括由相位位置逻辑控制的相位插值装置，它通过数字低通滤波器从时钟数据恢复环路的本地相位更新信号中获取其更新信号。 接收机还提供全局相位更新源选择逻辑，以控制哪个时钟数据恢复环路正在分发相位更新信息，哪个时钟数据恢复环路正在接收基于时钟分析块的相位更新信息。
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