-
公开(公告)号：US20090300338A1
公开(公告)日：2009-12-03
申请号：US12128332
申请日：2008-05-28
申请人： Paul Caprioli , Martin Karlsson , Gideon N. Levinsky , Khondakar A. Mujtaba , Shailender Chaudhry , Murali K. Inaganti
发明人： Paul Caprioli , Martin Karlsson , Gideon N. Levinsky , Khondakar A. Mujtaba , Shailender Chaudhry , Murali K. Inaganti
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3834 , G06F9/3863
摘要： Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing instructions before a checkpoint is generated. When executing instructions before the checkpoint is generated, the processor is configured to perform limited or no merging of stores into existing entries in the store queue. Then, upon detecting a predetermined condition, the processor is configured to generate a checkpoint. After generating the checkpoint, the processor is configured to continue to execute instructions. When executing instructions after the checkpoint is generated, the processor is configured to freely merge subsequent stores into post-checkpoint entries in the store queue.
摘要翻译： 本发明的实施例提供了一种处理器，其将存储结合在N入口先进先出（FIFO）存储队列中。 在这些实施例中，处理器通过在生成检查点之前执行指令来开始。 在生成检查点之前执行指令时，处理器被配置为对存储队列中的现有条目执行有限或不合并存储。 然后，在检测到预定条件时，处理器被配置为生成检查点。 生成检查点后，处理器配置为继续执行指令。 在检查点生成后执行指令时，处理器被配置为将后续存储自由合并到存储队列中的后检查点条目中。
-
公开(公告)号：US07934080B2
公开(公告)日：2011-04-26
申请号：US12128332
申请日：2008-05-28
申请人： Paul Caprioli , Martin Karlsson , Gideon N. Levinsky , Khondakar A. Mujtaba , Shailender Chaudhry , Murali K. Inaganti
发明人： Paul Caprioli , Martin Karlsson , Gideon N. Levinsky , Khondakar A. Mujtaba , Shailender Chaudhry , Murali K. Inaganti
IPC分类号： G06F9/312
CPC分类号： G06F9/3842 , G06F9/3834 , G06F9/3863
摘要： Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing instructions before a checkpoint is generated. When executing instructions before the checkpoint is generated, the processor is configured to perform limited or no merging of stores into existing entries in the store queue. Then, upon detecting a predetermined condition, the processor is configured to generate a checkpoint. After generating the checkpoint, the processor is configured to continue to execute instructions. When executing instructions after the checkpoint is generated, the processor is configured to freely merge subsequent stores into post-checkpoint entries in the store queue.
摘要翻译： 本发明的实施例提供了一种处理器，其将存储结合在N入口先进先出（FIFO）存储队列中。 在这些实施例中，处理器通过在生成检查点之前执行指令来开始。 在生成检查点之前执行指令时，处理器被配置为对存储队列中的现有条目执行有限或不合并存储。 然后，在检测到预定条件时，处理器被配置为产生检查点。 生成检查点后，处理器配置为继续执行指令。 在检查点生成后执行指令时，处理器被配置为将后续存储自由合并到存储队列中的后检查点条目中。
-
公开(公告)号：US09146744B2
公开(公告)日：2015-09-29
申请号：US12116009
申请日：2008-05-06
CPC分类号： G06F9/3826 , G06F9/383 , G06F9/3842 , G06F9/3855
摘要： Embodiments of the present invention provide a system which executes a load instruction or a store instruction. During operation the system receives a load instruction. The system then determines if an unrestricted entry or a restricted entry in a store queue contains data that satisfies the load instruction. If not, the system retrieves data for the load instruction from a cache. If so, the system conditionally forwards data from the unrestricted entry or the restricted entry by: (1) forwarding data from an unrestricted entry that contains the youngest store that satisfies the load instruction when any number of unrestricted or restricted entries contain data that satisfies the load instruction; (2) forwarding data from an unrestricted entry when only one restricted entry and no unrestricted entries contain data that satisfies the load instruction; and (3) deferring the load instruction by placing the load instruction in a deferred queue when two or more restricted entries and no unrestricted entries contain data that satisfies the load instruction.
摘要翻译： 本发明的实施例提供一种执行加载指令或存储指令的系统。 在运行过程中，系统接收到一个加载指令。 然后，系统确定存储队列中的无限制条目或限制条目是否包含满足加载指令的数据。 如果没有，系统将从缓存中检索加载指令的数据。 如果是这样，系统通过以下方式有条件地转发来自非限制条目或限制条目的数据：（1）当任何数量的无限制或限制条目包含满足条件的数据时，从包含满足加载指令的最小存储的无限制条目转发数据 加载指令; （2）当只有一个限制条目和不限制条目包含满足加载指令的数据时，从非限制条目转发数据; 和（3）通过在两个或多个限制条目和不受限制的条目包含满足加载指令的数据的情况下将加载指令放置在延迟队列中来推迟加载指令。
-
公开(公告)号：US20090282225A1
公开(公告)日：2009-11-12
申请号：US12116009
申请日：2008-05-06
IPC分类号： G06F9/312
CPC分类号： G06F9/3826 , G06F9/383 , G06F9/3842 , G06F9/3855
摘要： Embodiments of the present invention provide a system which executes a load instruction or a store instruction. During operation the system receives a load instruction. The system then determines if an unrestricted entry or a restricted entry in a store queue contains data that satisfies the load instruction. If not, the system retrieves data for the load instruction from a cache. If so, the system conditionally forwards data from the unrestricted entry or the restricted entry by: (1) forwarding data from an unrestricted entry that contains the youngest store that satisfies the load instruction when any number of unrestricted or restricted entries contain data that satisfies the load instruction; (2) forwarding data from an unrestricted entry when only one restricted entry and no unrestricted entries contain data that satisfies the load instruction; and (3) deferring the load instruction by placing the load instruction in a deferred queue when two or more restricted entries and no unrestricted entries contain data that satisfies the load instruction.
摘要翻译： 本发明的实施例提供一种执行加载指令或存储指令的系统。 在运行过程中，系统接收到一个加载指令。 然后，系统确定存储队列中的无限制条目或限制条目是否包含满足加载指令的数据。 如果没有，系统将从缓存中检索加载指令的数据。 如果是这样，系统通过以下方式有条件地转发来自非限制条目或限制条目的数据：（1）当任何数量的无限制或限制条目包含满足条件的数据时，从包含满足加载指令的最小存储的无限制条目转发数据 加载指令; （2）当只有一个限制条目和不限制条目包含满足加载指令的数据时，从非限制条目转发数据; 和（3）通过在两个或多个限制条目和不受限制的条目包含满足加载指令的数据的情况下将加载指令放置在延迟队列中来推迟加载指令。
-
公开(公告)号：US08484434B2
公开(公告)日：2013-07-09
申请号：US13402796
申请日：2012-02-22
IPC分类号： G06F13/12
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
摘要翻译： 本发明的实施例提供一种生成高速缓冲存储器的索引的系统。 系统通过接收访问高速缓冲存储器的请求开始，其中请求包括地址信息。 然后系统获得与请求相关联的非地址信息。 接下来，系统使用地址信息和非地址信息来生成索引。 然后，系统使用索引来实现对高速缓存的访问。
-
6.发明授权Using address and non-address information for improved index generation for cache memories 有权使用地址和非地址信息来改进高速缓存存储器的索引生成公开(公告)号：US08151084B2
公开(公告)日：2012-04-03
申请号：US12018407
申请日：2008-01-23
IPC分类号： G06F12/10
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
摘要翻译： 本发明的实施例提供一种生成高速缓冲存储器的索引的系统。 系统通过接收访问高速缓冲存储器的请求开始，其中请求包括地址信息。 然后系统获得与请求相关联的非地址信息。 接下来，系统使用地址信息和非地址信息来生成索引。 然后，系统使用索引来实现对高速缓存的访问。
-
公开(公告)号：US20120166756A1
公开(公告)日：2012-06-28
申请号：US13402796
申请日：2012-02-22
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
摘要翻译： 本发明的实施例提供一种生成高速缓冲存储器的索引的系统。 系统通过接收访问高速缓冲存储器的请求开始，其中请求包括地址信息。 然后系统获得与请求相关联的非地址信息。 接下来，系统使用地址信息和非地址信息来生成索引。 然后，系统使用索引来实现对高速缓存的访问。
-
公开(公告)号：US20090187906A1
公开(公告)日：2009-07-23
申请号：US12018417
申请日：2008-01-23
IPC分类号： G06F9/46
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3851 , G06F9/3863
摘要： Embodiments of the present invention provide a system that facilitates transactional execution in a processor. The system starts by executing program code for a thread in a processor. Upon detecting a predetermined indicator, the system starts a transaction for a section of the program code for the thread. When starting the transaction, the system executes a checkpoint instruction. If the checkpoint instruction is a WEAK_CHECKPOINT instruction, the system executes a semi-ordered transaction. During the semi-ordered transaction, the system preserves code atomicity but not memory atomicity. Otherwise, the system executes a regular transaction. During the regular transaction, the system preserves both code atomicity and memory atomicity.
摘要翻译： 本发明的实施例提供一种促进处理器中的事务执行的系统。 系统通过为处理器中的线程执行程序代码来启动。 在检测到预定指示符时，系统针对线程的程序代码的一部分开始事务。 开始事务时，系统执行检查点指令。 如果检查点指令是WEAK_CHECKPOINT指令，则系统执行半订单事务。 在半订单事务期间，系统保留代码原子性，但不保留内存原子性。 否则，系统将执行常规事务。 在常规事务期间，系统保留代码原子性和内存原子性。
-
公开(公告)号：US20090187727A1
公开(公告)日：2009-07-23
申请号：US12018407
申请日：2008-01-23
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
摘要翻译： 本发明的实施例提供一种生成高速缓冲存储器的索引的系统。 系统通过接收访问高速缓冲存储器的请求开始，其中请求包括地址信息。 然后系统获得与请求相关联的非地址信息。 接下来，系统使用地址信息和非地址信息来生成索引。 然后，系统使用索引来实现对高速缓存的访问。
-
10.发明授权Selectively defering load instructions after encountering a store instruction with an unknown destination address during speculative execution 有权在推测执行期间遇到具有未知目的地地址的存储指令后，选择性地推迟加载指令公开(公告)号：US08601240B2
公开(公告)日：2013-12-03
申请号：US12773661
申请日：2010-05-04
IPC分类号： G06F9/312
CPC分类号： G06F9/3842 , G06F9/3832 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3863
摘要： The described embodiments provide a system for executing instructions in a processor. While executing instructions in an execute-ahead mode, the processor encounters a store instruction for which a destination address is unknown. The processor then defers the store instruction. Upon encountering a load instruction while the store instruction with the unknown destination address is deferred, the processor determines if the load instruction is to continue executing. If not, the processor defers the load instruction. Otherwise, the processor continues executing the load instruction.
摘要翻译： 所描述的实施例提供了一种用于在处理器中执行指令的系统。 当以执行方式执行指令时，处理器遇到目标地址未知的存储指令。 然后，处理器延迟存储指令。 当具有未知目的地地址的存储指令被延迟时遇到加载指令，处理器确定加载指令是否继续执行。 如果没有，则处理器延迟加载指令。 否则，处理器继续执行加载指令。
-
-
-
-
-
-
-
-
-
搜索结果
219 条记录 (耗时 0.028 秒)
