Anti-prefetch instruction
    1.
    发明授权
    Anti-prefetch instruction 有权
    反预取指令

    公开(公告)号:US08732438B2

    公开(公告)日:2014-05-20

    申请号:US12104159

    申请日:2008-04-16

    IPC分类号: G06F9/30

    摘要: Embodiments of the present invention execute an anti-prefetch instruction. These embodiments start by decoding instructions in a decode unit in a processor to prepare the instructions for execution. Upon decoding an anti-prefetch instruction, these embodiments stall the decode unit to prevent decoding subsequent instructions. These embodiments then execute the anti-prefetch instruction, wherein executing the anti-prefetch instruction involves: (1) sending a prefetch request for a cache line in an L1 cache; (2) determining if the prefetch request hits in the L1 cache; (3) if the prefetch request hits in the L1 cache, determining if the cache line contains a predetermined value; and (4) conditionally performing subsequent operations based on whether the prefetch request hits in the L1 cache or the value of the data in the cache line.

    摘要翻译: 本发明的实施例执行反预取指令。 这些实施例首先解码处理器中的解码单元中的指令,以准备执行指令。 在对反预取指令进行解码时,这些实施例使解码单元停止以防止解码后续指令。 这些实施例然后执行反预取指令,其中执行反预取指令涉及:(1)在L1高速缓存中发送用于高速缓存行的预取请求; (2)确定预取请求是否在L1高速缓存中命中; (3)如果预取请求命中在L1高速缓存中,则确定高速缓存线是否包含预定值; 以及(4)基于所述预提取请求是否在所述L1高速缓存中的命中或所述高速缓存行中的数据的值有条件地执行后续操作。

    AGGRESSIVE STORE MERGING IN A PROCESSOR THAT SUPPORTS CHECKPOINTING
    3.
    发明申请
    AGGRESSIVE STORE MERGING IN A PROCESSOR THAT SUPPORTS CHECKPOINTING 有权
    在支持检查的处理器中进行积极的存储合并

    公开(公告)号:US20090300338A1

    公开(公告)日:2009-12-03

    申请号:US12128332

    申请日:2008-05-28

    IPC分类号: G06F9/30

    摘要: Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing instructions before a checkpoint is generated. When executing instructions before the checkpoint is generated, the processor is configured to perform limited or no merging of stores into existing entries in the store queue. Then, upon detecting a predetermined condition, the processor is configured to generate a checkpoint. After generating the checkpoint, the processor is configured to continue to execute instructions. When executing instructions after the checkpoint is generated, the processor is configured to freely merge subsequent stores into post-checkpoint entries in the store queue.

    摘要翻译: 本发明的实施例提供了一种处理器,其将存储结合在N入口先进先出(FIFO)存储队列中。 在这些实施例中,处理器通过在生成检查点之前执行指令来开始。 在生成检查点之前执行指令时,处理器被配置为对存储队列中的现有条目执行有限或不合并存储。 然后,在检测到预定条件时,处理器被配置为生成检查点。 生成检查点后,处理器配置为继续执行指令。 在检查点生成后执行指令时,处理器被配置为将后续存储自由合并到存储队列中的后检查点条目中。

    METHOD AND APPARATUS FOR DETERMINING CACHE STORAGE LOCATIONS BASED ON LATENCY REQUIREMENTS
    4.
    发明申请
    METHOD AND APPARATUS FOR DETERMINING CACHE STORAGE LOCATIONS BASED ON LATENCY REQUIREMENTS 有权
    基于延迟要求确定缓存存储位置的方法和装置

    公开(公告)号:US20100299482A1

    公开(公告)日:2010-11-25

    申请号:US12470639

    申请日:2009-05-22

    IPC分类号: G06F12/08 G06F12/00 G06F12/10

    摘要: A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.

    摘要翻译: 公开了一种用于以快速方式或缓存方式存储二进制信息的方法。 该方法包括接收要存储在具有多个方式的高速缓冲存储器中的二进制信息块。 多种方式包括方法的第一子集和方法的第二子集,其中来自第一方法子集之一的第一执行核心的高速缓存访​​问具有比来自第二子集的第二子集 方法。 该方法还包括基于预定访问等待时间和与二进制信息块相关联的一个或多个参数确定是否将二进制信息块存储为第一组方式之一或第二组路径之一。

    Method and apparatus for determining cache storage locations based on latency requirements
    5.
    发明授权
    Method and apparatus for determining cache storage locations based on latency requirements 有权
    基于延迟要求确定缓存存储位置的方法和装置

    公开(公告)号:US08065485B2

    公开(公告)日:2011-11-22

    申请号:US12470639

    申请日:2009-05-22

    IPC分类号: G06F12/00 G06F9/26

    摘要: A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.

    摘要翻译: 公开了一种用于以快速方式或缓存方式存储二进制信息的方法。 该方法包括接收要存储在具有多个方式的高速缓冲存储器中的二进制信息块。 多种方式包括方法的第一子集和方法的第二子集,其中来自第一方法子集之一的第一执行核心的高速缓存访​​问具有比来自第二子集的第二子集 方法。 该方法还包括基于预定访问等待时间和与二进制信息块相关联的一个或多个参数确定是否将二进制信息块存储为第一组方式之一或第二组路径之一。

    HANDLING A STORE INSTRUCTION WITH AN UNKNOWN DESTINATION ADDRESS DURING SPECULATIVE EXECUTION
    6.
    发明申请
    HANDLING A STORE INSTRUCTION WITH AN UNKNOWN DESTINATION ADDRESS DURING SPECULATIVE EXECUTION 有权
    在行政执行期间处理未知的目的地地址

    公开(公告)号:US20110276791A1

    公开(公告)日:2011-11-10

    申请号:US12773661

    申请日:2010-05-04

    IPC分类号: G06F9/312

    摘要: The described embodiments provide a system for executing instructions in a processor. While executing instructions in an execute-ahead mode, the processor encounters a store instruction for which a destination address is unknown. The processor then defers the store instruction. Upon encountering a load instruction while the store instruction with the unknown destination address is deferred, the processor determines if the load instruction is to continue executing. If not, the processor defers the load instruction. Otherwise, the processor continues executing the load instruction.

    摘要翻译: 所描述的实施例提供了一种用于在处理器中执行指令的系统。 当以执行方式执行指令时,处理器遇到目标地址未知的存储指令。 然后,处理器延迟存储指令。 当具有未知目的地地址的存储指令被延迟时遇到加载指令,处理器确定加载指令是否继续执行。 如果没有,则处理器延迟加载指令。 否则,处理器继续执行加载指令。

    Aggressive store merging in a processor that supports checkpointing
    7.
    发明授权
    Aggressive store merging in a processor that supports checkpointing 有权
    积极的商店合并在支持检查点的处理器中

    公开(公告)号:US07934080B2

    公开(公告)日:2011-04-26

    申请号:US12128332

    申请日:2008-05-28

    IPC分类号: G06F9/312

    摘要: Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing instructions before a checkpoint is generated. When executing instructions before the checkpoint is generated, the processor is configured to perform limited or no merging of stores into existing entries in the store queue. Then, upon detecting a predetermined condition, the processor is configured to generate a checkpoint. After generating the checkpoint, the processor is configured to continue to execute instructions. When executing instructions after the checkpoint is generated, the processor is configured to freely merge subsequent stores into post-checkpoint entries in the store queue.

    摘要翻译: 本发明的实施例提供了一种处理器,其将存储结合在N入口先进先出(FIFO)存储队列中。 在这些实施例中,处理器通过在生成检查点之前执行指令来开始。 在生成检查点之前执行指令时,处理器被配置为对存储队列中的现有条目执行有限或不合并存储。 然后,在检测到预定条件时,处理器被配置为产生检查点。 生成检查点后,处理器配置为继续执行指令。 在检查点生成后执行指令时,处理器被配置为将后续存储自由合并到存储队列中的后检查点条目中。

    Store queue having restricted and unrestricted entries
    9.
    发明授权
    Store queue having restricted and unrestricted entries 有权
    存储队列具有受限和不受限制的条目

    公开(公告)号:US09146744B2

    公开(公告)日:2015-09-29

    申请号:US12116009

    申请日:2008-05-06

    摘要: Embodiments of the present invention provide a system which executes a load instruction or a store instruction. During operation the system receives a load instruction. The system then determines if an unrestricted entry or a restricted entry in a store queue contains data that satisfies the load instruction. If not, the system retrieves data for the load instruction from a cache. If so, the system conditionally forwards data from the unrestricted entry or the restricted entry by: (1) forwarding data from an unrestricted entry that contains the youngest store that satisfies the load instruction when any number of unrestricted or restricted entries contain data that satisfies the load instruction; (2) forwarding data from an unrestricted entry when only one restricted entry and no unrestricted entries contain data that satisfies the load instruction; and (3) deferring the load instruction by placing the load instruction in a deferred queue when two or more restricted entries and no unrestricted entries contain data that satisfies the load instruction.

    摘要翻译: 本发明的实施例提供一种执行加载指令或存储指令的系统。 在运行过程中,系统接收到一个加载指令。 然后,系统确定存储队列中的无限制条目或限制条目是否包含满足加载指令的数据。 如果没有,系统将从缓存中检索加载指令的数据。 如果是这样,系统通过以下方式有条件地转发来自非限制条目或限制条目的数据:(1)当任何数量的无限制或限制条目包含满足条件的数据时,从包含满足加载指令的最小存储的无限制条目转发数据 加载指令; (2)当只有一个限制条目和不限制条目包含满足加载指令的数据时,从非限制条目转发数据; 和(3)通过在两个或多个限制条目和不受限制的条目包含满足加载指令的数据的情况下将加载指令放置在延迟队列中来推迟加载指令。

    Dynamic sizing of translation lookaside buffer for power reduction
    10.
    发明授权
    Dynamic sizing of translation lookaside buffer for power reduction 有权
    用于功率降低的翻译后备缓冲器的动态尺寸

    公开(公告)号:US08595464B2

    公开(公告)日:2013-11-26

    申请号:US13183164

    申请日:2011-07-14

    IPC分类号: G06F12/10

    摘要: Methods and mechanisms for operating a translation lookaside buffer (TLB). A translation lookaside buffer (TLB) includes a plurality of segments, each segment including one or more entries. A control unit is coupled to the TLB. The control unit is configured to determine utilization of segments, and dynamically disable segments in response to determining that segments are under-utilized. The control unit is also configured to dynamically enable segments responsive to determining a given number of segments are over-utilized.

    摘要翻译: 用于操作翻译后备缓冲器(TLB)的方法和机制。 翻译后备缓冲器(TLB)包括多个段,每个段包括一个或多个条目。 控制单元耦合到TLB。 控制单元被配置为确定段的利用率,并且响应于确定段未被利用而动态地禁用段。 控制单元还被配置为响应于确定给定数量的段被过度利用来动态地启用段。