公开(公告)号：US06823019B1

公开(公告)日：2004-11-23

申请号：US09363005

申请日：1999-07-30

申请人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith

发明人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith

IPC分类号： H04B1406

CPC分类号： H03H17/04

摘要： DC transients are removed from a digital filter such as a sigma delta filter (in particular from a sigma delta high pass filter) from the outset by presetting an input summing node to a sigma delta modulator. While the input summing node may be preset using any appropriate input, in a disclosed embodiment, a sigma delta high pass filter is preset by switching a partial feedback term between an input containing the non-zero preset value and the normal input comprising the output from the input summing node. The preset value is chosen based on the value of the zero of the transfer function of the sigma delta high pass filter, e.g., with the complement of the gain factor.

摘要翻译： 通过将输入求和节点预设到Σ-Δ调制器，从一开始就从数字滤波器例如Σ-Δ滤波器（特别是从Σ-Δ高通滤波器）中去除DC瞬变。 虽然可以使用任何适当的输入来预设输入求和节点，但是在所公开的实施例中，通过在包含非零预设值的输入和包括输出的正常输入之间切换部分反馈项来预设Σ-Δ高通滤波器 输入求和节点。 基于Σ-Δ高通滤波器的传递函数的零值的值例如以增益因子的补数来选择预设值。

公开(公告)号：US06625278B1

公开(公告)日：2003-09-23

申请号：US09379603

申请日：1999-08-24

申请人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith ,  Steven B. Witmer

发明人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith ,  Steven B. Witmer

IPC分类号： H04M100

CPC分类号： H04M11/062 ,  H04M1/76

摘要： An AC impedance matching architecture which provides programmable AC impedance matching in a given range using a digital filter to filter a signal fed back from the impedance matched line to generate an AC impedance emulation control signal. The AC impedance emulation control signal is combined with a transmit signal (if desired) and drives a voltage controlled current source, which is in parallel with a reference impedance. A voltage is developed across the reference impedance to drive, e.g., the telephone line. The reference impedance is chosen based on a desired maximum AC impedance. The gain of the digital filter, a first order sigma delta filter in the disclosed embodiment, is chosen based on the desired value of the AC impedance. The transfer function of the digital filter is derived based on a desired AC impedance.

摘要翻译： AC阻抗匹配架构，其使用数字滤波器在给定范围内提供可编程AC阻抗匹配，以对从阻抗匹配线反馈的信号进行滤波，以产生AC阻抗仿真控制信号。 交流阻抗仿真控制信号与发射信号（如果需要）组合，并驱动与参考阻抗并联的压控电流源。 在参考阻抗上产生电压以驱动例如电话线。 基于所需的最大AC阻抗来选择参考阻抗。 在所公开的实施例中，数字滤波器，第一级Σ-Δ滤波器的增益是基于AC阻抗的期望值来选择的。 基于所需的AC阻抗导出数字滤波器的传递函数。

公开(公告)号：US06232900B1

公开(公告)日：2001-05-15

申请号：US09299089

申请日：1999-04-26

申请人： Paul D. Hendricks ,  Lane A. Smith

发明人： Paul D. Hendricks ,  Lane A. Smith

IPC分类号： H03M300

CPC分类号： H03H17/0411

摘要： A 2nd order digital filter requiring only one sigma delta modulator is created by implementing (1) a 2nd order feedforward term created by the cascade of two 1st order elements; (2) a 2nd order feedback term created by the cascade of two 1st order elements; and (3) another 2nd order feedback term created by the cascade of two more 1st order elements to eliminate the need for another sigma delta modulator to provide a 2nd order filter. Thus, for the mere ‘cost’ of additional feedback loops, which are small in comparison with the size and complexity of another sigma delta modulator, a second sigma delta modulator is not necessary to implement a 2nd order digital filter in accordance with the principles with the present invention.

摘要翻译： 仅需要一个Σ-Δ调制器的二阶数字滤波器通过实现（1）由两个1阶元件级联产生的二阶前馈项来产生; （2）由两个一阶元素级联产生的二阶反馈项; 和（3）由两个以上的第一级元件的级联产生的另一个二阶反馈项，以消除另一个Σ-Δ调制器提供二阶滤波器的需要。 因此，对于与另一个Σ-Δ调制器的尺寸和复杂度相比较小的附加反馈回路的“成本”，第二个Σ-Δ调制器不需要根据以下原则实现二阶数字滤波器： 本发明。

公开(公告)号：US06674856B1

公开(公告)日：2004-01-06

申请号：US09401995

申请日：1999-09-23

申请人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith ,  Steven B. Witmer

发明人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith ,  Steven B. Witmer

IPC分类号： H04M100

CPC分类号： H04M1/68

摘要： The present invention provides a digital pre-distortion filter in arrangement with a data access arrangement (DAA) on the component side (e.g., in a modem chipset). This arrangement of the pre-distortion filter outside of the DAA allows digital processes such as digital emulation of the central office impedance to remain unaffected by the pre-distortion in the transmitted signal, allowing the dynamic range of the transmitted signal to be flattened to minimize return loss without complicating the transfer function of the digital emulation of the central office complex load. In the case of a digital emulation filter, placement of a digital pre-distortion filter outside of an analog-to-digital (A/D) digital-to-analog (D/A) loop also minimizes the noise otherwise associated with the use of a pre-distortion filter. Thus, benefits of a pre-distortion filter can be gained without interfering with emulation of impedance, and without causing a significant amount of noise in the transmitted signal.

摘要翻译： 本发明提供了一种数字预失真滤波器，其配置为在组件侧（例如，调制解调器芯片组）中的数据访问装置（DAA）。 DAA之前的预失真滤波器的这种布置允许诸如中心局阻抗的数字仿真的数字处理不受传输信号中的预失真的影响，允许传输信号的动态范围被平坦化以最小化 返回损耗，而不会使中心局复杂负载的数字仿真传输功能复杂化。 在数字仿真滤波器的情况下，数字预失真滤波器在模数（A / D）数模（D / A）环路之外的放置也使得与使用相关的噪声最小化 的预失真滤波器。 因此，可以获得预失真滤波器的优点而不干扰阻抗的仿真，并且不会在发射信号中引起大量的噪声。

公开(公告)号：US20140068122A1

公开(公告)日：2014-03-06

申请号：US13604048

申请日：2012-09-05

申请人： Qiao Shen ,  Samuel Khoo ,  Wen Zhu ,  Lane A. Smith

发明人： Qiao Shen ,  Samuel Khoo ,  Wen Zhu ,  Lane A. Smith

IPC分类号： G06F13/14

CPC分类号： G06F13/4204 ,  Y02D10/14 ,  Y02D10/151

摘要： Methods, systems and processor-readable media for reducing the width of a logical comparison. A width of a logical comparison based on a previous result generated can be recursively reduced from a data stream and a maximum count of consecutive ones or consecutive zeros determined from the serial data stream based on a priority encoder within a single clock cycle in order to avoid a use of complex functions. In this manner, the maximum number of the consecutive ones or the consecutive zeros in a parallel word bus within the single dock cycle can be ascertained.

摘要翻译： 用于减少逻辑比较宽度的方法，系统和处理器可读介质。 基于生成的先前结果的逻辑比较的宽度可以从单个时钟周期内的基于优先级编码器的数据流和从串行数据流确定的连续零的最大计数递归地减少，以避免 使用复杂的功能。 以这种方式，可以确定单个码头周期内的并行字总线中的连续零或连续零的最大数目。

公开(公告)号：US08219344B2

公开(公告)日：2012-07-10

申请号：US12789544

申请日：2010-05-28

申请人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith ,  Paul H. Tracy

发明人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith ,  Paul H. Tracy

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.

摘要翻译： 提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。 通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。 可以使用所确定的控制信号来开始压控延迟环路。 可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。

公开(公告)号：US20120170621A1

公开(公告)日：2012-07-05

申请号：US12968538

申请日：2011-01-03

申请人： Paul Tracy ,  Mohammad Mobin ,  Ye Liu ,  Lane A. Smith

发明人： Paul Tracy ,  Mohammad Mobin ,  Ye Liu ,  Lane A. Smith

IPC分类号： H04B1/38

CPC分类号： H04L25/03038

摘要： In described embodiments, a transceiver includes an eye monitor, clock and data recovery, and adaptation modules. Data sampling clock phase and error clock phase determined from a data eye are decoupled in the transceiver during a sampling phase correction process. Decoupling these clock phases during the sampling phase correction process allows relative optimization of system equalization parameters without degradation of various adaptation algorithms. Such adaptation algorithms might be employed for received signal gain and equalization such as, for example, Decision Feedback Equalizer (DFE) adaptation. Deriving the data sampling clock and error clock phases from the same clock generation source and with independent clock control enables an iterative sampling phase correction process that allows for accelerated clock and data recovery (CDR) without disturbing the data eye shape.

摘要翻译： 在所描述的实施例中，收发器包括眼睛监视器，时钟和数据恢复以及适配模块。 在采样相位校正过程中，从数据眼睛确定的数据采样时钟相位和误差时钟相位在收发器中解耦。 在采样相位校正过程中去耦合这些时钟相位允许系统均衡​​参数的相对优化，而不会降低各种自适应算法。 这样的适配算法可以用于接收信号增益和均衡，例如，判决反馈均衡器（DFE）适配。 从相同的时钟产生源和独立的时钟控制中获取数据采样时钟和错误时钟相位，可以实现迭代采样相位校正过程，可以在不影响数据眼睛形状的情况下加速时钟和数据恢复（CDR）。

公开(公告)号：US08165253B2

公开(公告)日：2012-04-24

申请号：US12200106

申请日：2008-08-28

申请人： Christopher J. Abel ,  Vladimir Sindalovsky ,  Lane A. Smith

发明人： Christopher J. Abel ,  Vladimir Sindalovsky ,  Lane A. Smith

IPC分类号： H04L7/00

CPC分类号： H04J3/0685

摘要： Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal.

摘要翻译： 提供串行器/解串器发射机同步的方法和装置。 通过在一个或多个信道中产生同步请求，在一个或多个串行器/解串器设备中同步多个信道; 响应于所述同步请求产生使能信号; 以及响应于使能信号，仅产生一个同步信号的一个或多个周期的门控同步信号。 门控同步信号可以可选地在同步信号的一个或多个周期之后被断言。

公开(公告)号：US07848473B2

公开(公告)日：2010-12-07

申请号：US11020021

申请日：2004-12-22

申请人： Ronald L. Freyman ,  Vladimir Sindalovsky ,  Lane A. Smith

发明人： Ronald L. Freyman ,  Vladimir Sindalovsky ,  Lane A. Smith

IPC分类号： H04L7/04

CPC分类号： H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0337

摘要： A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal. In addition, according to the present invention, the roaming tap interpolator includes a delay unit that selectively delays one or more of the first signal and the second signal to generate an interpolation signal, the interpolation signal selectively having a first phase or a second phase.

摘要翻译： 公开了一种基于漫游抽头内插器来产生相位控制数据的方法和装置。 本发明认识到，漫游抽头内插器在每个内插区域的边界处具有固有的非线性和不连续性。 公开了一种漫游抽头内插器，其在时间上偏移插值曲线，以避免插值曲线中的不需要的伪影。 漫游抽头内插器通常包括多个延迟元件，其延迟第一信号以产生每个具有相关联的相位的多个内插区域; 多路复用器，用于选择一个或多个插值区域; 以及内插器，用于处理所选择的一个或多个内插区域以产生第二信号。 此外，根据本发明，漫游抽头内插器包括延迟单元，其选择性地延迟第一信号和第二信号中的一个或多个以产生内插信号，该内插信号选择性地具有第一相位或第二相位。

公开(公告)号：US20100128828A1

公开(公告)日：2010-05-27

申请号：US12323155

申请日：2008-11-25

申请人： Mohammad S. Mobin ,  Kenneth W. Paist ,  Lane A. Smith

发明人： Mohammad S. Mobin ,  Kenneth W. Paist ,  Lane A. Smith

IPC分类号： H04B1/10

CPC分类号： H04L25/03006 ,  H04L2025/0349

摘要： Methods and apparatus are provided for adapting one or more equalization parameters in a communications system by reducing group delay spread. According to one aspect of the invention, one or more equalization parameters in a communications system are adapted by detecting one or more predefined run length patterns in a received signal, such as a plurality of consecutive same-valued bits; evaluating a transition latch value for each of the detected predefined run length patterns, wherein the transition latch value provides an indication of whether the received signal is under-equalized or over-equalized; and adjusting the one or more equalization parameters of the communications system based on the evaluation of the transition latch value. The adjusted equalization parameters may be employed to equalize intersymbol interference. A data eye monitor can be employed to evaluate the transition latch value.

摘要翻译： 提供了用于通过减少组延迟扩展来调整通信系统中的一个或多个均衡参数的方法和装置。 根据本发明的一个方面，通信系统中的一个或多个均衡参数通过检测接收信号中的一个或多个预定义的游程长度模式来适配，诸如多个连续的同值比特; 评估所检测到的预定游程长度模式中的每一个的转换锁存值，其中所述转换锁存值提供所述接收信号是否欠均衡或过均衡的指示; 以及基于所述转换锁存器值的评估来调整所述通信系统的一个或多个均衡参数。 可以采用经调整的均衡参数来均衡码间干扰。 数据眼监视器可用于评估转换锁存值。