Distributed switch
    1.
    发明申请
    Distributed switch 有权
    分布式交换机

    公开(公告)号:US20050063354A1

    公开(公告)日:2005-03-24

    申请号:US10653030

    申请日:2003-08-29

    CPC分类号: G11B33/126 G11B33/128

    摘要: A computer system comprises a plurality of shelves. Each shelf has a carrier for removably receiving a plurality of information processing modules and a switching module. Each shelf also has an interconnection member for providing connections between the information processing modules and the switching module. The switching modules of the respective shelves are interconnected in a logical stacking configuration to form a logical stacking arrangement.

    摘要翻译: 计算机系统包括多个货架。 每个搁架具有用于可拆卸地接收多个信息处理模块和切换模块的载体。 每个搁架还具有用于提供信息处理模块和切换模块之间的连接的互连构件。 各个搁板的交换模块以逻辑堆叠配置互连以形成逻辑堆叠布置。

    Aggregation switch
    2.
    发明申请
    Aggregation switch 有权
    聚合开关

    公开(公告)号:US20050047098A1

    公开(公告)日:2005-03-03

    申请号:US10653029

    申请日:2003-08-29

    CPC分类号: G11B33/126 G11B33/128

    摘要: A computer system comprises a plurality of shelves. Each shelf has a carrier for removably receiving a plurality of information processing modules and a switching module. Each shelf also has an interconnection member for providing connections between the information processing modules and the switching module. The shelves are logically connected into a plurality of stacks, the switching modules of the respective shelves in each stack being interconnected in a logical stacking configuration. The computer system further comprises a shelf having a carrier for removably receiving a master switching module, wherein the master switching module is connected into each stack as a common master switch for all of the stacks

    摘要翻译: 计算机系统包括多个货架。 每个搁架具有用于可拆卸地接收多个信息处理模块和切换模块的载体。 每个搁架还具有用于提供信息处理模块和切换模块之间的连接的互连构件。 搁板逻辑上连接到多个堆叠中,每个堆叠中的相应搁板的交换模块以逻辑堆叠配置互连。 计算机系统还包括具有用于可拆卸地接收主交换模块的载体的机架,其中主交换模块连接到每个堆叠中作为用于所有堆栈的公共主交换机

    Method and apparatus for separating and isolating control of processing entities in a network interface
    3.
    发明授权
    Method and apparatus for separating and isolating control of processing entities in a network interface 有权
    用于分离和隔离网络接口中处理实体的控制的方法和装置

    公开(公告)号:US07992144B1

    公开(公告)日:2011-08-02

    申请号:US11098195

    申请日:2005-04-04

    IPC分类号: G06F15/16 G06F9/455

    摘要: A network system that provides for separating and isolating control of processing entities in a network interface. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. One of the processing entities operates as a hypervisor to configure control resources to isolate operation of the plurality of data processing partitions to process data transported by the network system. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing. In various embodiments of the invention, the asymmetrical data processing partitions can comprise a plurality of processor cores, a single processor core, a combination of strands of an individual processor core or a single strand of an individual processor core. The asymmetrical data processing partitions are scalable by adding additional processing entities.

    摘要翻译: 一种网络系统,用于分离和隔离网络接口中处理实体的控制。 网络接口单元可操作地连接到多个处理实体和定义共享存储器空间的多个存储器单元。 网络接口单元还包括存储器访问模块,其包括多个存储器访问通道,分组分类器和可操作以控制由网络传送的数据的处理的多个调度控制模块。 其中一个处理实体作为管理程序来配置控制资源以隔离多个数据处理分区的操作,以处理网络系统传输的数据。 分组分类器可操作以提供分组与多个非对称数据处理之间的关联。 在本发明的各种实施例中,非对称数据处理分区可以包括多个处理器核心,单个处理器核心,单个处理器核心的线束组合或单个处理器核心的单个链路的组合。 不对称数据处理分区可通过添加附加处理实体进行扩展。

    Method and apparatus for arbitrarily mapping functions to preassigned processing entities in a network system
    4.
    发明授权
    Method and apparatus for arbitrarily mapping functions to preassigned processing entities in a network system 有权
    将功能任意映射到网络系统中的预分配处理实体的方法和装置

    公开(公告)号:US07889734B1

    公开(公告)日:2011-02-15

    申请号:US11098063

    申请日:2005-04-05

    IPC分类号: H04L12/28

    CPC分类号: H04L12/56 H04L47/10

    摘要: A method and apparatus for mapping sessions to preassigned processing entities in a network system. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions based upon an association with a predetermined session. In various embodiments of the invention, the asymmetrical data processing partitions can comprise a plurality of processor cores, a single processor core, a combination of strands of an individual processor core or a single strand of an individual processor core. The asymmetrical data processing partitions are scalable by adding additional processing entities.

    摘要翻译: 一种用于将会话映射到网络系统中的预分配处理实体的方法和装置。 网络接口单元可操作地连接到多个处理实体和定义共享存储器空间的多个存储器单元。 网络接口单元还包括存储器访问模块,其包括多个存储器访问通道,分组分类器和可操作以控制由网络传送的数据的处理的多个调度控制模块。 在本发明的各种实施例中,多个处理实体中的预定子集可操作地与多个存储器单元中的预定子集相关联,从而定义多个非对称数据处理分区。 分组分类器可操作以基于与预定会话的关联来提供分组与多个非对称数据处理分区之间的关联。 在本发明的各种实施例中,非对称数据处理分区可以包括多个处理器核心,单个处理器核心,单个处理器核心的线束组合或单个处理器核心的单个链路的组合。 不对称数据处理分区可通过添加附加处理实体进行扩展。

    Distributed switch
    5.
    发明授权
    Distributed switch 有权
    分布式交换机

    公开(公告)号:US07415011B2

    公开(公告)日:2008-08-19

    申请号:US10653030

    申请日:2003-08-29

    IPC分类号: H04L12/28 H04L12/56

    CPC分类号: G11B33/126 G11B33/128

    摘要: A computer system comprises a plurality of shelves. Each shelf has a carrier for removably receiving a plurality of information processing modules and a switching module. Each shelf also has an interconnection member for providing connections between the information processing modules and the switching module. The switching modules of the respective shelves are interconnected in a logical stacking configuration to form a logical stacking arrangement.

    摘要翻译: 计算机系统包括多个货架。 每个搁架具有用于可拆卸地接收多个信息处理模块和切换模块的载体。 每个搁架还具有用于提供信息处理模块和切换模块之间的连接的互连构件。 各个搁板的交换模块以逻辑堆叠配置互连以形成逻辑堆叠布置。

    Method and apparatus for zero-copy receive buffer management
    6.
    发明授权
    Method and apparatus for zero-copy receive buffer management 有权
    用于零拷贝接收缓冲区管理的方法和装置

    公开(公告)号:US07142540B2

    公开(公告)日:2006-11-28

    申请号:US10198923

    申请日:2002-07-18

    IPC分类号: H04L12/28

    摘要: An apparatus and method for managing the receipt of communication traffic in the form of packets or other units. The apparatus includes a communication interface (e.g., a NIC, a TCA) coupled to one or more host computer systems. Through Direct Memory Access (DMA) operations, the interface reassembles payloads of received packets into host buffers based on their sequence numbers, without buffering them in the interface. Packet headers are separated from the payloads and passed to a host for protocol processing after the payload DMA is completed. Host buffers may be of virtually any size. For each communication connection, state information is maintained on the interface, which may identify an upper level protocol so that an upper level protocol header is passed to the host as part of the packet header, not as part of the payload. Protocol termination remains in the host.

    摘要翻译: 一种用于以分组或其他单元的形式管理接收通信业务的装置和方法。 该装置包括耦合到一个或多个主机系统的通信接口(例如,NIC,TCA)。 通过直接存储器访问(DMA)操作,接口将接收到的数据包的有效载荷根据其序列号重新组合到主机缓冲区中,而不会在接口中缓存它们。 分组报头与有效载荷分离,并在有效载荷DMA完成后传递给主机进行协议处理。 主机缓冲区可能几乎是任何大小。 对于每个通信连接,在接口上维护状态信息,其可以标识上级协议,使得上级协议报头作为分组报头的一部分而不是作为有效载荷的一部分传递到主机。 协议终止保留在主机中。

    Server blade for performing load balancing functions
    7.
    发明授权
    Server blade for performing load balancing functions 有权
    服务器刀片,用于执行负载平衡功能

    公开(公告)号:US07032037B2

    公开(公告)日:2006-04-18

    申请号:US10215667

    申请日:2002-08-09

    IPC分类号: G06F13/00

    摘要: A modular computer system may be provided. The modular computer system may comprise a carrier operable removably to receive a plurality of computer system modules therein. A plurality of information processing modules can be removably received in the carrier, each module may have a communications port operable to connect to a communications network internal to the carrier. The modular computer system may also comprise a switch operable to connect to the internal communications network to distribute information messages between the modules and to connect to an external communications network. An information distribution module may be provided removably received in the carrier operable connect to the internal communications network to receive an information message, to perform processing on the message to determine a destination, and to forward the message toward the determined destination via the internal communications network.

    摘要翻译: 可以提供模块化计算机系统。 模块化计算机系统可以包括可移除地可操作地在其中接收多个计算机系统模块的载体。 多个信息处理模块可以被可移除地接收在载体中,每个模块可以具有可操作以连接到载体内部的通信网络的通信端口。 模块化计算机系统还可以包括可操作以连接到内部通信网络以在模块之间分发信息消息并连接到外部通信网络的交换机。 信息分配模块可以被提供可拆卸地接收在载体中,可操作地连接到内部通信网络以接收信息消息,对消息执行处理以确定目的地,并且经由内部通信网络向确定的目的地转发消息 。

    Method and apparatus for a multi-gigabit ethernet architecture
    8.
    发明授权
    Method and apparatus for a multi-gigabit ethernet architecture 有权
    用于多吉比特以太网架构的方法和装置

    公开(公告)号:US06873630B1

    公开(公告)日:2005-03-29

    申请号:US09314782

    申请日:1999-05-19

    摘要: An Ethernet architecture is provided for connecting a computer system or other network entity to a dedicated Ethernet network medium. The network interface enables the transmission and receipt of data by striping individual Ethernet frames across a plurality of logical channels and may thus operate at substantially the sum of the individual channel rates. Each channel may be conveyed by a separate conductor (e.g., in a bundle) or the channels may be carried simultaneously on a shared medium (e.g., an electrical or optical conductor that employs a form of multiplexing). On a sending station, a distributor within the sender's network interface receives Ethernet frames (e.g., from a MAC) and distributes frame bytes in a round-robin fashion on the plurality of channels. Each “mini-frame” is separately framed and encoded for transmission across its channel. On a receiving station, the receiver's network interface includes a collector for collecting the multiple mini-frames (e.g., after decoding) and reconstructing the frame's byte stream (e.g., for transfer to the receiver's MAC). The first and last bytes of each frame and mini-frame are marked for ease of recognition. Multiple unique idle symbols may be employed for transmission during inter-packet gaps to facilitate the collector's synchronization of the multiple channels and/or enhance error detection. A maximum channel skew is specified, and each received channel may be buffered with an elasticity that is proportional to the maximum skew so that significant propagation delay may be encountered between channels without disrupting communications.

    摘要翻译: 提供了一种用于将计算机系统或其他网络实体连接到专用以太网网络介质的以太网架构。 网络接口通过跨多个逻辑信道划分单个以太网帧来实现数据的传输和接收,并且因此可以基本上以各个信道速率的总和来操作。 每个通道可以由单独的导体(例如,束)传送,或者可以在共享介质(例如采用多路复用形式的电或光导体)上同时携带通道。 在发送站上,发送者网络接口内的分发者接收以太网帧(例如,从MAC),并以循环方式在多个信道上分配帧字节。 每个“迷你帧”被单独成帧和编码以在其信道上传输。 在接收站,接收机的网络接口包括用于收集多个迷你帧(例如,在解码之后)并重构帧的字节流(例如,用于传送到接收机的MAC)的收集器。 每个帧和小帧的第一个和最后一个字节被标记为易于识别。 可以采用多个唯一的空闲符号来进行间隔间间隔期间的传输,以便收集器同步多个信道和/或增强错误检测。 指定最大信道偏移,并且每个接收信道可以以与最大偏移成比例的弹性来缓冲,使得可以在通道之间遇到显着的传播延迟而不中断通信。

    Highly integrated multi-layer switch element architecture
    9.
    发明授权
    Highly integrated multi-layer switch element architecture 失效
    高度集成的多层交换元件架构

    公开(公告)号:US06246680B1

    公开(公告)日:2001-06-12

    申请号:US08884704

    申请日:1997-06-30

    IPC分类号: H04L1256

    摘要: An architecture for a highly integrated network element building block is provided. According to one aspect of the present invention, a network device building block includes a network interface with multiple ports for transmitting and receiving packets over a network. The network device building block also includes a packet buffer storage which is coupled to the network interface. The packet buffer storage acts as an elasticity buffer for adapting between incoming and outgoing bandwidth requirements. A shared memory manager may also be provided dynamically allocate and deallocate buffers in the packet buffer storage on behalf of the network interface and other clients of the packet buffer storage. The network device building block further includes a switch fabric which is coupled to the network interface. The switch fabric provides forwarding decisions for received packets. A given forwarding decision includes a list of ports upon which a particular received packet is to be forwarded. A central processing unit (CPU) interface is also included in the network device building block. The CPU interface is coupled to the switch fabric and is configured to forward packets received from the CPU based upon forwarding decisions provided by the switch fabric.

    摘要翻译: 提供了一种高度集成的网络元件构建块的架构。 根据本发明的一个方面,网络设备构建块包括具有多个端口的网络接口,用于经由网络发送和接收分组。 网络设备构建块还包括耦合到网络接口的分组缓冲存储器。 分组缓冲存储器用作弹性缓冲器,用于适应进入和传出带宽要求。 还可以提供共享存储器管理器,代表分组缓冲存储器的网络接口和其他客户端动态地分配和释放分组缓冲存储器中的缓冲区。 网络设备构建块还包括耦合到网络接口的交换结构。 交换结构为接收到的数据包提供转发决策。 给定的转发决定包括要在其上转发特定接收分组的端口列表。 中央处理单元(CPU)接口也包括在网络设备构建块中。 CPU接口耦合到交换结构,并且被配置为基于由交换结构提供的转发决定来转发从CPU接收的分组。

    Distributed VLAN mechanism for packet field replacement in a
multi-layered switched network element using a control field/signal for
indicating modification of a packet with a database search engine
    10.
    发明授权
    Distributed VLAN mechanism for packet field replacement in a multi-layered switched network element using a control field/signal for indicating modification of a packet with a database search engine 失效
    使用控制字段/信号指示数据库搜索引擎修改数据包的多层交换网元中的分组字段替换的分布式VLAN机制

    公开(公告)号:US6128666A

    公开(公告)日:2000-10-03

    申请号:US885000

    申请日:1997-06-30

    摘要: A system and method for updating packet headers using hardware that maintains the high performance of the network element. In one embodiment, the system includes an input port process (IPP) that buffers the input packet received and forwards header information to the search engine. The search engine searches a database maintained on the switch element to determine the type of the packet. In one embodiment, the type may indicate whether the packet can be routed in hardware. In another embodiment, the type may indicate whether the packet supports VLANs. The search engine sends the packet type information to the IPP along with the destination address (DA) to be updated if the packet is to be routed, or a VLAN tag if the packet has been identified to be forwarded to a particular VLAN. The IPP, during transmission of the packet to a packet memory selectively replaces the corresponding fields, e.g., DA field or VLAN tag field; the modified packet is stored in the packet memory. Associated with the packet memory are control fields containing control field information conveyed to the packet memory by the IPP. An output port process (OPP) reads the modified input packet and the control field information and selectively performs additional modifications to the modified input packet and issue control signals to the output interface (i.e., MAC). The MAC, based upon the control signals, replaces the source address field with the address of the MAC and generates a CRC that is appended to the end of the packet.

    摘要翻译: 一种用于使用维持网络元件的高性能的硬件来更新分组报头的系统和方法。 在一个实施例中,该系统包括缓冲所接收的输入分组的输入端口处理(IPP),并将头部信息转发到搜索引擎。 搜索引擎搜索在switch元素上维护的数据库以确定数据包的类型。 在一个实施例中,该类型可以指示分组是否可以在硬件中路由。 在另一个实施例中,该类型可以指示分组是否支持VLAN。 搜索引擎将分组类型信息与要进行路由的分组要更新的目标地址(DA)一起发送到IPP,如果分组已被标识为转发到特定VLAN,则将其发送到VLAN标签。 在将分组传输到分组存储器期间,IPP选择性地替换相应的字段,例如DA字段或VLAN标签字段; 修改的分组被存储在分组存储器中。 与分组存储器相关联的是包含由IPP传送到分组存储器的控制字段信息的控制字段。 输出端口处理(OPP)读取修改的输入分组和控制字段信息,并且选择性地对修改的输入分组执行附加修改,并向输出接口(即MAC)发出控制信号。 MAC基于控制信号,将源地址字段替换为MAC的地址,并生成附加到数据包末尾的CRC。