摘要:
A computer system comprises a plurality of shelves. Each shelf has a carrier for removably receiving a plurality of information processing modules and a switching module. Each shelf also has an interconnection member for providing connections between the information processing modules and the switching module. The switching modules of the respective shelves are interconnected in a logical stacking configuration to form a logical stacking arrangement.
摘要:
A computer system comprises a plurality of shelves. Each shelf has a carrier for removably receiving a plurality of information processing modules and a switching module. Each shelf also has an interconnection member for providing connections between the information processing modules and the switching module. The shelves are logically connected into a plurality of stacks, the switching modules of the respective shelves in each stack being interconnected in a logical stacking configuration. The computer system further comprises a shelf having a carrier for removably receiving a master switching module, wherein the master switching module is connected into each stack as a common master switch for all of the stacks
摘要:
A network system that provides for separating and isolating control of processing entities in a network interface. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. One of the processing entities operates as a hypervisor to configure control resources to isolate operation of the plurality of data processing partitions to process data transported by the network system. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing. In various embodiments of the invention, the asymmetrical data processing partitions can comprise a plurality of processor cores, a single processor core, a combination of strands of an individual processor core or a single strand of an individual processor core. The asymmetrical data processing partitions are scalable by adding additional processing entities.
摘要:
A method and apparatus for mapping sessions to preassigned processing entities in a network system. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions based upon an association with a predetermined session. In various embodiments of the invention, the asymmetrical data processing partitions can comprise a plurality of processor cores, a single processor core, a combination of strands of an individual processor core or a single strand of an individual processor core. The asymmetrical data processing partitions are scalable by adding additional processing entities.
摘要:
A computer system comprises a plurality of shelves. Each shelf has a carrier for removably receiving a plurality of information processing modules and a switching module. Each shelf also has an interconnection member for providing connections between the information processing modules and the switching module. The switching modules of the respective shelves are interconnected in a logical stacking configuration to form a logical stacking arrangement.
摘要:
An apparatus and method for managing the receipt of communication traffic in the form of packets or other units. The apparatus includes a communication interface (e.g., a NIC, a TCA) coupled to one or more host computer systems. Through Direct Memory Access (DMA) operations, the interface reassembles payloads of received packets into host buffers based on their sequence numbers, without buffering them in the interface. Packet headers are separated from the payloads and passed to a host for protocol processing after the payload DMA is completed. Host buffers may be of virtually any size. For each communication connection, state information is maintained on the interface, which may identify an upper level protocol so that an upper level protocol header is passed to the host as part of the packet header, not as part of the payload. Protocol termination remains in the host.
摘要:
A modular computer system may be provided. The modular computer system may comprise a carrier operable removably to receive a plurality of computer system modules therein. A plurality of information processing modules can be removably received in the carrier, each module may have a communications port operable to connect to a communications network internal to the carrier. The modular computer system may also comprise a switch operable to connect to the internal communications network to distribute information messages between the modules and to connect to an external communications network. An information distribution module may be provided removably received in the carrier operable connect to the internal communications network to receive an information message, to perform processing on the message to determine a destination, and to forward the message toward the determined destination via the internal communications network.
摘要:
An Ethernet architecture is provided for connecting a computer system or other network entity to a dedicated Ethernet network medium. The network interface enables the transmission and receipt of data by striping individual Ethernet frames across a plurality of logical channels and may thus operate at substantially the sum of the individual channel rates. Each channel may be conveyed by a separate conductor (e.g., in a bundle) or the channels may be carried simultaneously on a shared medium (e.g., an electrical or optical conductor that employs a form of multiplexing). On a sending station, a distributor within the sender's network interface receives Ethernet frames (e.g., from a MAC) and distributes frame bytes in a round-robin fashion on the plurality of channels. Each “mini-frame” is separately framed and encoded for transmission across its channel. On a receiving station, the receiver's network interface includes a collector for collecting the multiple mini-frames (e.g., after decoding) and reconstructing the frame's byte stream (e.g., for transfer to the receiver's MAC). The first and last bytes of each frame and mini-frame are marked for ease of recognition. Multiple unique idle symbols may be employed for transmission during inter-packet gaps to facilitate the collector's synchronization of the multiple channels and/or enhance error detection. A maximum channel skew is specified, and each received channel may be buffered with an elasticity that is proportional to the maximum skew so that significant propagation delay may be encountered between channels without disrupting communications.
摘要:
An architecture for a highly integrated network element building block is provided. According to one aspect of the present invention, a network device building block includes a network interface with multiple ports for transmitting and receiving packets over a network. The network device building block also includes a packet buffer storage which is coupled to the network interface. The packet buffer storage acts as an elasticity buffer for adapting between incoming and outgoing bandwidth requirements. A shared memory manager may also be provided dynamically allocate and deallocate buffers in the packet buffer storage on behalf of the network interface and other clients of the packet buffer storage. The network device building block further includes a switch fabric which is coupled to the network interface. The switch fabric provides forwarding decisions for received packets. A given forwarding decision includes a list of ports upon which a particular received packet is to be forwarded. A central processing unit (CPU) interface is also included in the network device building block. The CPU interface is coupled to the switch fabric and is configured to forward packets received from the CPU based upon forwarding decisions provided by the switch fabric.
摘要:
A system and method for updating packet headers using hardware that maintains the high performance of the network element. In one embodiment, the system includes an input port process (IPP) that buffers the input packet received and forwards header information to the search engine. The search engine searches a database maintained on the switch element to determine the type of the packet. In one embodiment, the type may indicate whether the packet can be routed in hardware. In another embodiment, the type may indicate whether the packet supports VLANs. The search engine sends the packet type information to the IPP along with the destination address (DA) to be updated if the packet is to be routed, or a VLAN tag if the packet has been identified to be forwarded to a particular VLAN. The IPP, during transmission of the packet to a packet memory selectively replaces the corresponding fields, e.g., DA field or VLAN tag field; the modified packet is stored in the packet memory. Associated with the packet memory are control fields containing control field information conveyed to the packet memory by the IPP. An output port process (OPP) reads the modified input packet and the control field information and selectively performs additional modifications to the modified input packet and issue control signals to the output interface (i.e., MAC). The MAC, based upon the control signals, replaces the source address field with the address of the MAC and generates a CRC that is appended to the end of the packet.