公开(公告)号：US20050024113A1

公开(公告)日：2005-02-03

申请号：US10604554

申请日：2003-07-30

申请人： Paul Kartschoke ,  Stephen Kosonocky ,  Randy Mann ,  Norman Rohrer

发明人： Paul Kartschoke ,  Stephen Kosonocky ,  Randy Mann ,  Norman Rohrer

IPC分类号： H03K3/037 ,  H03K3/356

CPC分类号： H03K3/356104 ,  H03K3/0375

摘要： In a first aspect, a cross-coupled inverter is provided that includes a first inverter circuit having a first NFET coupled to a first PFET and a second inverter circuit having a second NFET coupled to a second PFET. The second inverter circuit is cross-coupled with the first inverter circuit at a plurality of nodes. The body of at least one of the first NFET, the second NFET, the first PFET and the second PFET is coupled so as to form a feedback path that reduces discharging at one or more of the plurality of nodes in response to a soft error event at the cross-coupled inverter.

摘要翻译： 在第一方面，提供一种交叉耦合的反相器，其包括具有耦合到第一PFET的第一NFET的第一反相器电路和具有耦合到第二PFET的第二NFET的第二反相器电路。 第二逆变器电路在多个节点处与第一反相器电路交叉耦合。 第一NFET，第二NFET，第一PFET和第二PFET中的至少一个的主体被耦合以形成反馈路径，其减少响应于软错误事件的多个节点中的一个或多个的放电 在交叉耦合的逆变器。

公开(公告)号：US20050012045A1

公开(公告)日：2005-01-20

申请号：US10604416

申请日：2003-07-18

申请人： John Fifield ,  Paul Kartschoke ,  William KIaasen ,  Stephen Kosonocky ,  Randy Mann ,  Jeffery Oppold ,  Norman Rohrer

发明人： John Fifield ,  Paul Kartschoke ,  William KIaasen ,  Stephen Kosonocky ,  Randy Mann ,  Jeffery Oppold ,  Norman Rohrer

IPC分类号： G01J1/00 ,  G11C11/412

CPC分类号： G11C11/4125

摘要： A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches. A first embodiment of the detector circuit differentially detects the floating voltages of first and second silicon wells during periods of non-operation of the circuits fabricated in the first and second silicon wells. In a second embodiment, a detector circuit monitors the background voltage level of a single silicon well over first and second consecutive periods of time. A second application for the detection circuit is for traditional logic circuits.

摘要翻译： 一种用于检测硅阱电压或电流以指示硅阱的α粒子或宇宙射线冲击的检测器电路和方法。 本发明的检测电路的一个重要应用是用于SRAM中的冗余修复锁存器。 冗余修复锁存器在上电时通常写入一次，以记录失败的锁存数据，并且通常不会再次写入。 如果其中一个锁存器由于SER（软错误率（例如α粒子或宇宙射线的击穿））事件而改变状态，则SRAM的冗余锁存器中的修复数据现在将被错误地映射。 检测器电路和方法监视锁存器以发生SER事件，并且响应于此，将修复数据重新加载到冗余修复锁存器。 检测器电路的第一实施例在第一和第二硅阱中制造的电路的非操作期间差分地检测第一和第二硅阱的浮置电压。 在第二实施例中，检测器电路在第一和第二连续时间段内监测单个硅阱的背景电压电平。 检测电路的第二个应用是传统的逻辑电路。

公开(公告)号：US20080048711A1

公开(公告)日：2008-02-28

申请号：US11926386

申请日：2007-10-29

申请人： Kerry Bernstein ,  Philip Emma ,  John Fifield ,  Paul Kartschoke ,  William Klaasen ,  Norman Rohrer

发明人： Kerry Bernstein ,  Philip Emma ,  John Fifield ,  Paul Kartschoke ,  William Klaasen ,  Norman Rohrer

IPC分类号： H03K19/003

CPC分类号： H03K19/007

摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。

公开(公告)号：US20060026457A1

公开(公告)日：2006-02-02

申请号：US10710641

申请日：2004-07-27

申请人： Kerry Bernstein ,  Philip Emma ,  John Fifield ,  Paul Kartschoke ,  William Klaasen ,  Norman Rohrer

发明人： Kerry Bernstein ,  Philip Emma ,  John Fifield ,  Paul Kartschoke ,  William Klaasen ,  Norman Rohrer

IPC分类号： G06F11/00

CPC分类号： H03K19/007

摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。

公开(公告)号：US20050086620A1

公开(公告)日：2005-04-21

申请号：US10605683

申请日：2003-10-17

申请人： Paul Kartschoke ,  Norman Rohrer

发明人： Paul Kartschoke ,  Norman Rohrer

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5045

摘要： A method (200, 300, 400, 500) utilizing available timing slack in the various timing paths (108) of a synchronous integrated circuit (104) to reduce the overall instantaneous current draw across the circuit. In the method, each timing path is analyzed to determine its late mode margin or its late mode margin and early mode margin. A delay is added to each timing path having a late mode margin greater than zero. In one embodiment, the delay is equal to the corresponding late mode margin. In another embodiment, the delay is equal to the difference between the corresponding late and early mode margins. Each delay effectively shifts the peak current draw for the corresponding timing path within each clock cycle so that the peaks do not occur simultaneously across all timing paths. In other embodiments, the peak overall instantaneous current draw can be further reduced by reducing the delay in some of the delayed timing paths.

摘要翻译： 一种在同步集成电路（104）的各种定时路径（108）中利用可用的定时松弛的方法（200,300,400,500）来减少整个电路上的总瞬时电流消耗。 在该方法中，分析每个定时路径以确定其延迟模式余量或其延迟模式余量和早期模式余量。 延迟增加到具有大于零的延迟模式余量的每个定时路径。 在一个实施例中，延迟等于相应的延迟模式余量。 在另一个实施例中，延迟等于相应的延迟和早期模式余量之间的差异。 每个延迟有效地移动每个时钟周期内对应的时序路径的峰值电流消耗，使得峰值不会在所有定时路径上同时发生。 在其他实施例中，可以通过减少一些延迟定时路径中的延迟来进一步减小峰值总瞬时电流消耗。

公开(公告)号：US20050278662A1

公开(公告)日：2005-12-15

申请号：US10709798

申请日：2004-05-28

申请人： Paul Kartschoke ,  Thomas Mitchell ,  Norman Rohrer ,  Ronald Rose

发明人： Paul Kartschoke ,  Thomas Mitchell ,  Norman Rohrer ,  Ronald Rose

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5036

摘要： A method is disclosed for preventing circuit failures due to gate oxide leakage, and is used to efficiently check many nets of a circuit on a chip or within a macro to find logical fails due to gate oxide leakage using DC calculations, wherein the gate leakage is treated as a noise source for a static noise analysis of the circuit.

摘要翻译： 公开了一种用于防止由于栅极氧化物泄漏引起的电路故障的方法，并且用于有效地检查芯片上或宏中的电路的许多网络，以便使用DC计算由于栅极氧化物泄漏而发现逻辑故障，其中栅极泄漏为 作为电路的静态噪声分析的噪声源。

公开(公告)号：US20060208760A1

公开(公告)日：2006-09-21

申请号：US11407176

申请日：2006-04-19

申请人： Kerry Bernstein ,  Norman Rohrer

发明人： Kerry Bernstein ,  Norman Rohrer

IPC分类号： H03K19/0175

CPC分类号： G06F17/505 ,  H03K19/0016 ,  H03K19/0948

摘要： A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly low input state; wherein the logic stages having the predominantly high input state, comprise one or more thin gate dielectric and high threshold voltage PFETs with respect to a reference PFET and one or more thick gate dielectric and low threshold voltage NFETs with respect to a reference NFET; and wherein the logic stages having the predominantly low input state, comprise one or more thick gate dielectric and low threshold voltage PFETs with respect to the reference PFET and one or more thin gate dielectric and high threshold voltage NFETs with respect to the reference NFET.

公开(公告)号：US20070162446A1

公开(公告)日：2007-07-12

申请号：US11275533

申请日：2006-01-12

申请人： David Appenzeller ,  Frances Clougherty ,  James Garris ,  Kort Longenbach ,  Bruce Ogilvie ,  Dean Percy ,  Norman Rohrer ,  William Tanona ,  Mario Theberge ,  Jin Wu

发明人： David Appenzeller ,  Frances Clougherty ,  James Garris ,  Kort Longenbach ,  Bruce Ogilvie ,  Dean Percy ,  Norman Rohrer ,  William Tanona ,  Mario Theberge ,  Jin Wu

IPC分类号： G06F17/30

CPC分类号： G06F11/2236

摘要： A method of testing a multi-processor unit microprocessor. The method includes: (a) selecting and testing, with a selected parameter set of a group of parameter sets, a processor unit of a microprocessor having two or more processor units; (b) comparing the operation of the selected processor unit to a selected specification of a set of operational specifications of the microprocessor; (c) if the testing indicates that the operation of the selected processor unit does not meet the selected specification, repeating (a) and (b) with a different parameter set of the group of parameter sets until either the selected processor unit meets the selected specification or all parameter sets of the group of parameter sets have been selected; and (d) if the operation of the selected processor unit does meet the selected specification, repeating (a), (b) and (c) until all processor units have been selected.

摘要翻译： 一种测试多处理器单元微处理器的方法。 该方法包括：（a）使用一组参数组的选定参数集来选择和测试具有两个或多个处理器单元的微处理器的处理器单元; （b）将所选择的处理器单元的操作与微处理器的一组操作规范的选定规格进行比较; （c）如果测试指示所选择的处理器单元的操作不符合所选规格，则用参数组组的不同参数组重复（a）和（b），直到所选择的处理器单元满足所选择的规定 已经选择了参数组组的规范或所有参数集; 和（d）如果所选择的处理器单元的操作确实满足所选择的规范，则重复（a），（b）和（c），直到所有处理器单元被选择为止。

公开(公告)号：US20060012398A1

公开(公告)日：2006-01-19

申请号：US10710453

申请日：2004-07-13

申请人： Kerry Bernstein ,  Norman Rohrer

发明人： Kerry Bernstein ,  Norman Rohrer

IPC分类号： H03K19/096

CPC分类号： G06F17/505 ,  H03K19/0016 ,  H03K19/0948

摘要： A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly low input state; wherein the logic stages having the predominantly high input state, comprise one or more thin gate dielectric and high threshold voltage PFETs with respect to a reference PFET and one or more thick gate dielectric and low threshold voltage NFETs with respect to a reference NFET; and wherein the logic stages having the predominantly low input state, comprise one or more thick gate dielectric and low threshold voltage PFETs with respect to the reference PFET and one or more thin gate dielectric and high threshold voltage NFETs with respect to the reference NFET.

摘要翻译： 低泄漏单调CMOS逻辑电路及其设计方法，设计方法及设计方法。 该电路包括：一个或多个逻辑级，逻辑级中的至少一个具有主要高输入状态或具有主要低输入状态; 其中具有主要高输入状态的逻辑级包括相对于参考PFET和相对于参考NFET的一个或多个厚栅极电介质和低阈值电压NFET的一个或多个薄栅极电介质和高阈值电压PFET; 并且其中具有主要为低输入状态的逻辑级包括相对于参考PFET和相对于参考NFET的一个或多个薄栅极电介质和高阈值电压NFET的一个或多个厚栅极电介质和低阈值电压PFET。

公开(公告)号：US20060187596A1

公开(公告)日：2006-08-24

申请号：US10906563

申请日：2005-02-24

申请人： David Cain ,  Jeffrey Gambino ,  Norman Rohrer ,  Daryl Seitzer ,  Steven Voldman

发明人： David Cain ,  Jeffrey Gambino ,  Norman Rohrer ,  Daryl Seitzer ,  Steven Voldman

IPC分类号： H02H9/00

CPC分类号： H01L27/0251

摘要： An SOI integrated circuit includes ESD protection on an SOI chip. A first power domain and a second power domain are provided in the SOI chip. In one embodiment , a charge modulation network in the SOI chip between the first power domain and the second power domain mitigates accumulation of electrical charge in an electrically isolated region of the SOI chip. In another embodiment, an ESD protection device in the SOI chip electrically connects the first power domain and the second power domain via a low metal layer to provide a discharge path for accumulated charge.

摘要翻译： SOI集成电路包括在SOI芯片上的ESD保护。 在SOI芯片中提供第一功率域和第二功率域。 在一个实施例中，在第一功率域和第二功率域之间的SOI芯片中的电荷调制网络减轻了SOI芯片的电隔离区域中的电荷积累。 在另一个实施例中，SOI芯片中的ESD保护器件经由低金属层电连接第一功率域和第二功率域，以提供用于累积电荷的放电路径。