公开(公告)号：US07983181B1

公开(公告)日：2011-07-19

申请号：US11379866

申请日：2006-04-24

申请人： Paul Miranda ,  Larry D. Hewitt

发明人： Paul Miranda ,  Larry D. Hewitt

IPC分类号： H04L12/26

CPC分类号： H03M13/09 ,  H04L1/0061 ,  H04L25/14

摘要： A technique for negotiating the width of a link between a first device and a second device includes detecting, during initialization, a respective signal on one or more control lines associated with at least a portion of an N-bit link. The N-bit link is configured as a single link having a width of N or multiple sublinks having a width less than N based on a respective value of the respective signal on the one or more control lines.

摘要翻译： 用于协商第一设备和第二设备之间的链路的宽度的技术包括在初始化期间检测与N位链路的至少一部分相关联的一个或多个控制线上的相应信号。 基于一个或多个控制线上的相应信号的相应值，将N位链路配置为宽度为N的单个链路或宽度小于N的多个子链路。

公开(公告)号：US07146510B1

公开(公告)日：2006-12-05

申请号：US10198637

申请日：2002-07-18

申请人： Frank P. Helms ,  Derrick R. Meyer ,  Larry D. Hewitt ,  Dale E. Gulick ,  William A. Hughes ,  Scott E. Swanstrom

发明人： Frank P. Helms ,  Derrick R. Meyer ,  Larry D. Hewitt ,  Dale E. Gulick ,  William A. Hughes ,  Scott E. Swanstrom

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3296 ,  G06F9/30083 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/172

摘要： An integrated circuit is coupled to a communication link and to a separate signal line and includes programmable registers specifying communication link width and frequency. The integrated circuit responds to a change in the value of the signal line by changing the width and/or frequency of at least a portion of the communication link to the programmed value in response to a change in a logical value of the signal line, without the integrated circuit entering a reset state. The width and/or frequency may be changed during a POST routine or during system operation as part of a power management or other system function while maintaining its operational state.

摘要翻译： 集成电路耦合到通信链路和单独的信号线，并且包括指定通信链路宽度和频率的可编程寄存器。 通过将通信链路的至少一部分的宽度和/或频率响应于信号线的逻辑值的改变而改变为编程值，集成电路响应于信号线的值的变化，而没有 集成电路进入复位状态。 宽度和/或频率可以在POST程序期间或在系统操作期间作为功率管理或其他系统功能的一部分而改变，同时保持其操作状态。

公开(公告)号：US06725297B1

公开(公告)日：2004-04-20

申请号：US10093146

申请日：2002-03-07

申请人： Tahsin Askar ,  Larry D. Hewitt ,  Eric G. Chambers

发明人： Tahsin Askar ,  Larry D. Hewitt ,  Eric G. Chambers

IPC分类号： G06F1300

CPC分类号： G06F13/128

摘要： A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.

摘要翻译： 用于计算机系统的I / O节点的外围接口电路。 一种用于计算机系统的输入/输出节点的外围接口电路包括第一缓冲电路，第二缓冲电路和总线接口电路。 第一缓冲电路接收分组命令，并且可以包括每个对应于多个虚拟通道的相应虚拟通道的第一多个缓冲器。 第二缓冲电路被耦合以从总线接口电路接收分组命令，并且可以包括每个对应于多个虚拟通道中的相应虚拟通道的第二多个缓冲器。 总线接口电路可以被配置为将存储在第一缓冲器电路中的选择的分组命令转换成适合于在外围总线上传输的命令。

公开(公告)号：US06697890B1

公开(公告)日：2004-02-24

申请号：US10034878

申请日：2001-12-27

申请人： Dale E. Gulick ,  Larry D. Hewitt

发明人： Dale E. Gulick ,  Larry D. Hewitt

IPC分类号： G06F1312

CPC分类号： G06F13/4247 ,  G06F13/4004

摘要： An I/O node for a computer system including an integrated I/O interface. An input/output node for a computer system that is implemented upon an integrated circuit includes a first transceiver unit, a second transceiver unit, a packet tunnel, a bridge unit and an I/O interface unit. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus. The second transceiver unit may receive and transmit packet transactions on a second link of the packet bus. The packet tunnel may convey selected packet transactions between the first and second transceiver units. The bridge unit may receive particular packet transactions from the first transceiver may transmit transactions corresponding to the particular packet transactions upon a peripheral bus. The I/O interface unit may receive additional packet transactions from the first transceiver unit and may transmit transactions corresponding to the additional packet transactions upon an I/O link.

摘要翻译： 一个包含集成I / O接口的计算机系统的I / O节点。 在集成电路上实现的用于计算机系统的输入/输出节点包括第一收发器单元，第二收发器单元，分组隧道，桥接单元和I / O接口单元。 第一收发器单元可以在分组总线的第一链路上接收和发送分组事务。 第二收发器单元可以在分组总线的第二链路上接收和发送分组事务。 分组隧道可以在第一和第二收发器单元之间传送所选择的分组事务。 桥接单元可以接收来自第一收发器的特定分组事务可以在外围总线上发送与特定分组事务相对应的事务。 I / O接口单元可以从第一收发器单元接收附加分组事务，并且可以在I / O链路上传送与附加分组事务相对应的事务。

公开(公告)号：US06385705B1

公开(公告)日：2002-05-07

申请号：US09702147

申请日：2000-10-30

申请人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

发明人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

IPC分类号： G06F1300

CPC分类号： G06F13/1621

摘要： A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access transactions further include first and second pipe identifications, respectively. The node circuit maps the first and second memory addresses to first and second node numbers, respectively. The first and second pipe identifications are compared. If the first and second pipe identifications compare equally, then the first and second node numbers are compared. First and second coherent memory access transactions are generated by the node coupled to the I/O bridge wherein the first and second coherent memory access transactions correspond to the first and second non-coherent memory access transactions, respectively. The first coherent memory access transaction is transmitted to one of the nodes of the multiprocessor computer system. However, the second coherent memory access transaction is not transmitted unless the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

公开(公告)号：US06202116B1

公开(公告)日：2001-03-13

申请号：US09098876

申请日：1998-06-17

申请人： Larry D. Hewitt

发明人： Larry D. Hewitt

IPC分类号： G06F1300

CPC分类号： G06F13/4273

摘要： A data bus is divided into two portions. One portion of the bus transfers data from one side of the bus to the other and the other portion of the bus transfers data in the opposite direction. Bus cycles that originate from one side of the bus only go in one direction (from the originator to the other side). In order to avoid inefficiency because one of the portions of the bus may become unused if a long bus cycle is going in one direction while nothing is being transferred in the opposite direction, one side can take over the whole data bus and transfer data over both sides of the bus.

摘要翻译： 数据总线分为两部分。 总线的一部分将数据从总线的一侧传输到另一侧，而总线的另一部分以相反的方向传输数据。 从总线一侧起始的总线循环只能沿一个方向（从始发者到另一方）。 为了避免低效率，因为如果长的总线周期在一个方向上进行而总线周期不会在相反的方向上传输，总线的一部分可能会变得不用，则一侧可以接管整个数据总线并且通过两者传输数据 公车两边。

公开(公告)号：US07334123B2

公开(公告)日：2008-02-19

申请号：US10429132

申请日：2003-05-02

申请人： Dale E. Gulick ,  Geoffrey S. Strongin ,  Larry D. Hewitt

发明人： Dale E. Gulick ,  Geoffrey S. Strongin ,  Larry D. Hewitt

IPC分类号： H04L9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F21/74 ,  G06F21/85 ,  G06F2221/2105

摘要： A computer system including a bus bridge for bridging transactions between a secure execution mode-capable processor and a security services processor. The bus bridge may include a transaction source detector, a configuration header and control logic. The transaction source detector may receive a security initialization transaction performed as a result of execution of a security initialization instruction. Further, the transaction source detector may determine whether the secure execution mode-capable processor is a source of the security initialization transaction. The configuration header may provide storage of information associated with the security services processor. The control logic may determine whether the security services processor is coupled to the bus bridge via a non-enumerable, peripheral bus. The control logic may also cause the configuration header to be accessible during a boot-up sequence in response to determining that the security services processor is coupled to the non-enumerable, peripheral bus.

摘要翻译： 一种计算机系统，包括用于桥接安全执行模式处理器和安全服务处理器之间的事务的总线桥。 总线桥可以包括事务源检测器，配置头和控制逻辑。 事务源检测器可以接收由于执行安全初始化指令而执行的安全初始化事务。 此外，事务源检测器可以确定安全执行模式处理器是否是安全初始化事务的源。 配置头可以提供与安全服务处理器相关联的信息的存储。 控制逻辑可以确定安全服务处理器是否经由不可枚举的外围总线耦合到总线桥。 响应于确定安全服务处理器耦合到不可枚举的外围总线，控制逻辑还可以使得配置头在引导序列期间可访问。

公开(公告)号：US06862647B1

公开(公告)日：2005-03-01

申请号：US10059691

申请日：2002-01-29

申请人： Larry D. Hewitt

发明人： Larry D. Hewitt

IPC分类号： G06F1/00 ,  G06F11/267

CPC分类号： G06F11/221

摘要： A system and method for observing transactions on a packet bus is disclosed. In one embodiment, a computer system includes a plurality of input/output (I/O) nodes serially coupled to a processor. Each of the I/O nodes may be configured to operate in a first (normal) mode, and a second (analysis) mode. During the normal mode, packets may be selectively conveyed through an I/O tunnel in the I/O node, and particular packets may be selectively conveyed to a peripheral bus interface in the I/O node. In the analysis mode, electrical signals corresponding to packets conveyed through the I/O tunnel may be replicated on a peripheral bus coupled to the peripheral bus interface. No conversion from the packet bus protocol to the peripheral bus protocol. A signal analyzer may be coupled to the peripheral bus, thereby allowing observation of the electrical signals.

摘要翻译： 公开了一种用于观察分组总线上的事务的系统和方法。 在一个实施例中，计算机系统包括串行耦合到处理器的多个输入/输出（I / O）节点。 每个I / O节点可以被配置为以第一（正常）模式和第二（分析）模式操作。 在正常模式期间，可以通过I / O节点中的I / O隧道选择性地传送分组，并且可以将特定分组选择性地传送到I / O节点中的外围总线接口。 在分析模式中，对应于通过I / O隧道传送的分组的电信号可以在耦合到外围总线接口的外围总线上复制。 无需从分组总线协议转换为外设总线协议。 信号分析器可以耦合到外围总线，从而允许观察电信号。

公开(公告)号：US06807599B2

公开(公告)日：2004-10-19

申请号：US09978349

申请日：2001-10-15

申请人： Stephen C. Ennis ,  Larry D. Hewitt

发明人： Stephen C. Ennis ,  Larry D. Hewitt

IPC分类号： G06F1300

CPC分类号： G06F13/128

摘要： A computer system I/O node. An input/output node for a computer system includes a first receiver unit configured to receive a first command on a first communication path and a first transmitter unit coupled to transmit a first corresponding command that corresponds to the first command on a second communication path. The input/output node also includes a second receiver unit configured to receive a second command on a third communication path and a second transmitter unit coupled to transmit a second corresponding command that corresponds to the second command on a fourth communication path. Further, the input/output node includes a bridge unit coupled to receive selected commands from the first receiver and the second receiver and configured to transmit commands corresponding to the selected commands upon a peripheral bus.

摘要翻译： 计算机系统I / O节点。 用于计算机系统的输入/输出节点包括被配置为在第一通信路径上接收第一命令的第一接收器单元和耦合以在第二通信路径上发送对应于第一命令的第一对应命令的第一发送器单元。 输入/输出节点还包括被配置为在第三通信路径上接收第二命令的第二接收器单元和耦合以在第四通信路径上发送对应于第二命令的第二对应命令的第二发送器单元。 此外，输入/输出节点包括耦合以从第一接收器和第二接收器接收所选命令的桥单元，并且被配置为在外围总线上发送与所选命令相对应的命令。

公开(公告)号：US06199132B1

公开(公告)日：2001-03-06

申请号：US09098854

申请日：1998-06-17

申请人： Larry D. Hewitt ,  Dale E. Gulick

发明人： Larry D. Hewitt ,  Dale E. Gulick

IPC分类号： G06F1300

CPC分类号： G06F13/4213

摘要： A bus transfers information including isochronous and asynchronous data between a first and a second integrated circuit. The bus guarantees a minimum bandwidth to isochronous data and also tries to minimize latency for isochronous data. The bus transfers data in asynchronous priority mode during a first portion of a first time period, wherein asynchronous data is transferred preferentially over isochronous data. Transfers over the bus selectably switch to isochronous priority mode for a second portion of the first time period in order to guarantee transfer of a predetermined amount of isochronous data during the first time period, thus guaranteeing the minimum bandwidth to isochronous data.

摘要翻译： 总线在第一和第二集成电路之间传送包括同步和异步数据的信息。 总线保证了同步数据的最小带宽，并且还尝试最小化同步数据的延迟。 总线在第一时间段的第一部分期间以异步优先模式传输数据，其中异步数据优先通过同步数据传送。 总线上的传输可选择地切换到第一时间段的第二部分的等时优先级模式，以便保证在第一时间段期间传送预定量的同步数据，从而保证对同步数据的最小带宽。