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1.发明授权Protecting the security of secure data sent from a central processor for processing by a further processing device 有权保护从中央处理器发送的安全数据的安全性，以便由另外的处理设备进行处理公开(公告)号：US08775824B2
公开(公告)日：2014-07-08
申请号：US12003858
申请日：2008-01-02
CPC分类号： G06F21/53 , G06F21/74 , G06F2221/2105
摘要： A data processing apparatus comprising: a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor in said non-secure mode, and processing data in said secure mode being performed under control of a secure operating system and processing data in said non-secure mode being performed under control of a non-secure operating system; and a further processing device for performing a task in response to a request from said data processor, said task comprising processing data at least some of which is secure data; wherein said further processing device is responsive to receipt of a signal to suspend said task to initiate: processing of said secure data using a secure key; and storage of said processed secure data to a non-secure data store; and is responsive to receipt of a signal to resume said task to initiate: retrieval of said processed secure data from said non-secure data store; and restoring of said processed secure data using said secure key; wherein said secure key is securely stored such that it is not accessible to other processes operating in said non-secure mode.
摘要翻译： 一种数据处理装置，包括：用于以安全和非安全模式处理数据的数据处理器，所述数据处理器处理所述安全模式中的数据，以访问在所述非安全模式下所述数据处理器不可访问的安全数据 并且在安全操作系统的控制下执行所述安全模式中的处理数据，并且在非安全操作系统的控制下执行所述非安全模式中的数据处理; 以及用于响应于来自所述数据处理器的请求执行任务的另一处理装置，所述任务包括处理数据，其中至少一些是安全数据; 其中所述另外的处理设备响应于收到信号以暂停所述任务以启动：使用安全密钥处理所述安全数据; 以及将所述处理的安全数据存储到非安全数据存储器; 并且响应于接收到信号以恢复所述任务以启动：从所述非安全数据存储中检索所述处理的安全数据; 以及使用所述安全密钥恢复所述处理的安全数据; 其中所述安全密钥被安全地存储，使得对于在所述非安全模式中操作的其他进程是不可访问的。
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2.发明申请Protecting the security of secure data sent from a central processor for processing by a further processing device 有权保护从中央处理器发送的安全数据的安全性，以便由另外的处理设备进行处理公开(公告)号：US20090172411A1
公开(公告)日：2009-07-02
申请号：US12003858
申请日：2008-01-02
IPC分类号： G06F12/14
CPC分类号： G06F21/53 , G06F21/74 , G06F2221/2105
摘要： A data processing apparatus comprising: a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor in said non-secure mode, and processing data in said secure mode being performed under control of a secure operating system and processing data in said non-secure mode being performed under control of a non-secure operating system; and a further processing device for performing a task in response to a request from said data processor, said task comprising processing data at least some of which is secure data; wherein said further processing device is responsive to receipt of a signal to suspend said task to initiate: processing of said secure data using a secure key; and storage of said processed secure data to a non-secure data store; and is responsive to receipt of a signal to resume said task to initiate: retrieval of said processed secure data from said non-secure data store; and restoring of said processed secure data using said secure key; wherein said secure key is securely stored such that it is not accessible to other processes operating in said non-secure mode.
摘要翻译： 一种数据处理装置，包括：用于以安全和非安全模式处理数据的数据处理器，所述数据处理器处理所述安全模式中的数据，以访问在所述非安全模式下所述数据处理器不可访问的安全数据 并且在安全操作系统的控制下执行所述安全模式中的处理数据，并且在非安全操作系统的控制下执行所述非安全模式中的数据处理; 以及用于响应于来自所述数据处理器的请求执行任务的另一处理装置，所述任务包括处理数据，其中至少一些是安全数据; 其中所述另外的处理设备响应于收到信号以暂停所述任务以启动：使用安全密钥处理所述安全数据; 以及将所述处理的安全数据存储到非安全数据存储器; 并且响应于接收到信号以恢复所述任务以启动：从所述非安全数据存储中检索所述处理的安全数据; 以及使用所述安全密钥恢复所述处理的安全数据; 其中所述安全密钥被安全地存储，使得对于在所述非安全模式中操作的其他进程是不可访问的。
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公开(公告)号：US08332660B2
公开(公告)日：2012-12-11
申请号：US12003857
申请日：2008-01-02
CPC分类号： G06F21/74 , G06F12/1491 , G06F21/72
摘要： A data processor for processing data in a secure mode having access to secure data that is not accessible to the data processor when processing data in the non-secure mode. A further processing device for performing a task in response to a request from the data processor issued from the non-secure mode. The further processing device including a secure data store not accessible to processes running on the data processor when in the non-secure mode. Prior to issuing requests, the data processor in the secure mode performs a set up operation on the further data processing device storing secure data in the secure data store. In response to receipt of the request from the data processor operating in the non-secure mode, the further data processing device performs the task using data stored in the secure data store to access any secure data required.
摘要翻译： 一种用于以安全模式处理数据的数据处理器，其具有在处理非安全模式下的数据时能够访问数据处理器不可访问的安全数据。 一种用于响应于从非安全模式发出的来自数据处理器的请求来执行任务的另外的处理装置。 所述另外的处理设备包括当处于非安全模式时在数据处理器上运行的进程不可访问的安全数据存储器。 在发出请求之前，以安全模式执行的数据处理器对存储安全数据存储中的安全数据的另外的数据处理装置执行建立操作。 响应于以非安全模式操作的数据处理器的请求的接收，另外的数据处理设备使用存储在安全数据存储器中的数据来执行任务以访问所需的任何安全数据。
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4.发明申请Cache device for coupling to a memory device and a method of operation of such a cache device 有权用于耦合到存储器件的缓存器件和这种高速缓存器件的操作方法公开(公告)号：US20110307664A1
公开(公告)日：2011-12-15
申请号：US12801484
申请日：2010-06-10
CPC分类号： G06F12/0895 , G06F12/121 , Y02D10/13
摘要： A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern. Upon detection of such an occurrence of a sequence of accesses by the regular access detection circuitry, an allocation policy employed by the cache to determine a selected cache line into which to store a data value is altered with the aim of increasing a likelihood that when an evicted data value output by the cache is subsequently written to the memory device, the associated memory location resides within an already activated block of memory locations. Hence, by detecting regular access patterns, and altering the allocation policy on detection of such patterns, this enables a reuse of already activated blocks within the memory device, thereby significantly improving memory utilisation, thereby giving rise to both performance improvements and power consumption reductions.
摘要翻译： 提供了一种缓存设备，用于在数据处理设备中用于存储由相关联的主设备访问的数据值。 每个数据值在存储器设备中具有相关联的存储器位置，并且存储器设备被布置为存储器位置的多个块，每个块必须在存储在该块中的任何数据值可被访问之前被激活。 高速缓存设备包括常规访问检测电路，用于检测对其相关联的存储器位置遵循规则模式的数据值的访问序列的发生。 在检测到常规访问检测电路的这种访问序列的发生时，高速缓存使用的用于确定存储数据值的所选高速缓存行的分配策略被改变，目的是增加当 由缓存输出的被驱逐的数据值随后被写入存储器件，相关联的存储器位置驻留在已经激活的存储器位置块中。 因此，通过检测常规访问模式，并且在检测到这种模式时改变分配策略，这使得能够在存储器设备内重新使用已激活的块，从而显着地提高存储器利用率，从而产生性能改善和功耗降低。
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公开(公告)号：US20090172329A1
公开(公告)日：2009-07-02
申请号：US12003857
申请日：2008-01-02
CPC分类号： G06F21/74 , G06F12/1491 , G06F21/72
摘要： A data processing apparatus comprising a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor processing data in said non-secure mode; and a further processing device for performing a task in response to a request from said data processor issued from said non-secure mode, said task comprising processing data at least some of which is secure data, said further processing device comprising a secure data store, said secure data store not being accessible to processes running on said data processor in non-secure mode; wherein prior to issuing any of said requests said data processor is adapted to perform a set up operation on said further data processing device, said set up operation being performed by said data processor operating in said secure mode and comprising storing secure data in said secure data store on said further processing device, said secure data being secure data required by said further processing device to perform said task; wherein in response to receipt of said request from said data processor operating in said non-secure mode said further data processing device performs said task using data stored in said secure data store to access any secure data required.
摘要翻译： 一种数据处理装置，包括用于以安全和非安全模式处理数据的数据处理器，所述数据处理器处理所述安全模式中的数据，以访问所述数据处理器不可访问的安全数据，所述数据处理器处理所述非安全 模式; 以及另外的处理装置，用于响应于从所述非安全模式发出的来自所述数据处理器的请求执行任务，所述任务包括处理数据，其中至少一些是安全数据，所述另外的处理装置包括安全数据存储， 所述安全数据存储器不能以非安全模式在所述数据处理器上运行的进程访问; 其中在发出任何所述请求之前，所述数据处理器适于对所述另外的数据处理设备执行建立操作，所述建立操作由所述数据处理器以所述安全模式操作并且包括将安全数据存储在所述安全数据中 存储在所述另外的处理设备上，所述安全数据是所述另外的处理设备执行所述任务所需的安全数据; 其中响应于以所述非安全模式操作的所述数据处理器接收到所述请求，所述另外的数据处理设备使用存储在所述安全数据存储器中的数据来执行所述任务以访问所需的任何安全数据。
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公开(公告)号：US5887129A
公开(公告)日：1999-03-23
申请号：US788286
申请日：1997-01-24
申请人： Paul Day , Nigel Charles Paver
发明人： Paul Day , Nigel Charles Paver
CPC分类号： G06F9/30083 , G06F1/32 , G06F9/30079 , G06F9/3869
摘要： The present invention provides an apparatus and method for processing data, the apparatus comprising a plurality of asynchronous control circuits, each asynchronous control circuit employing a request-acknowledge control loop to control data flow within that asynchronous control circuit, and being arranged to exchange data signals with at least one other of said plurality of asynchronous control circuits. Further, a first of said asynchronous control circuits includes a halt circuit for blocking a control signal in the control loop of the first asynchronous control circuit, thereby preventing the exchange of data signals with said at least one other of said plurality of asynchronous control circuits so as to cause the control loops of said plurality of asynchronous control circuits to become blocked. The present invention is based on an asynchronous design, which only causes transitions in the circuit in response to a request to carry out useful work. It can switch instantaneously between zero power dissipation and maximum performance upon demand. According to the invention, there is provided a `Halt` circuit which causes all processor activity to cease until an interrupt occurs. The circuit preferably works by intercepting a control signal in the processing apparatus' asynchronous control circuits, effectively breaking a single request-acknowledge control loop. Since the control circuits are interrelated, blocking the response in one loop rapidly (but not instantaneously) stalls all the other control loops in the apparatus, and hence the stall ultimately propagates throughout the entire apparatus, terminating all activity. Preferably, an interrupt is used to release the stall in the original control loop, and activity then propagates from this point throughout the system.
摘要翻译： 本发明提供了一种用于处理数据的装置和方法，该装置包括多个异步控制电路，每个异步控制电路采用一个请求确认控制环来控制该异步控制电路内的数据流，并且被配置为交换数据信号 与所述多个异步控制电路中的至少另一个异步控制电路。 此外，所述异步控制电路中的第一个包括用于阻塞第一异步控制电路的控制环路中的控制信号的停止电路，从而防止与所述多个异步控制电路中的所述至少另一个异步控制电路的数据信号的交换 以致所述多个异步控制电路的控制环路被阻塞。 本发明基于异步设计，其仅响应于执行有用工作的请求而引起电路中的转换。 它可以根据需要在零功耗和最大性能之间瞬间切换。 根据本发明，提供了一种“停止”电路，其使所有处理器的活动停止，直到发生中断。 该电路优选通过截取处理装置的异步控制电路中的控制信号而有效地破坏单个请求确认控制环路。 由于控制电路是相互关联的，所以在一个环路中快速（但不是瞬间）阻塞响应使设备中的所有其他控制环停止，因此失速最终在整个设备中传播，从而终止所有活动。 优选地，使用中断来释放原始控制回路中的停顿，然后从整个系统的这一点传播活动。
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公开(公告)号：US08001331B2
公开(公告)日：2011-08-16
申请号：US12081583
申请日：2008-04-17
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0215 , G06F12/121 , G06F12/127
摘要： A processing system 1 including a memory 10 and a cache memory 4 is provided with a page status unit 40 for providing a cache controller with a page open indication indicating one or more open pages of data values in memory. At least one of one or more cache management operations performed by the cache controller is responsive to the page open indication so that the efficiency and/or speed of the processing system can be improved.
摘要翻译： 包括存储器10和高速缓存存储器4的处理系统1设置有页面状态单元40，用于向高速缓存控制器提供指示存储器中数据值的一个或多个打开页面的页面打开指示。 高速缓存控制器执行的一个或多个高速缓存管理操作中的至少一个响应于页面打开指示，从而可以提高处理系统的效率和/或速度。
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8.发明授权Cache device for coupling to a memory device and a method of operation of such a cache device 有权用于耦合到存储器件的缓存器件和这种高速缓存器件的操作方法公开(公告)号：US08200902B2
公开(公告)日：2012-06-12
申请号：US12801484
申请日：2010-06-10
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/121 , Y02D10/13
摘要： A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern. Upon detection of such an occurrence of a sequence of accesses by the regular access detection circuitry, an allocation policy employed by the cache to determine a selected cache line into which to store a data value is altered with the aim of increasing a likelihood that when an evicted data value output by the cache is subsequently written to the memory device, the associated memory location resides within an already activated block of memory locations. Hence, by detecting regular access patterns, and altering the allocation policy on detection of such patterns, this enables a reuse of already activated blocks within the memory device, thereby significantly improving memory utilization, thereby giving rise to both performance improvements and power consumption reductions.
摘要翻译： 提供了一种缓存设备，用于在数据处理设备中用于存储由相关联的主设备访问的数据值。 每个数据值在存储器设备中具有相关联的存储器位置，并且存储器设备被布置为存储器位置的多个块，每个块必须在存储在该块中的任何数据值可被访问之前被激活。 高速缓存设备包括常规访问检测电路，用于检测对其相关联的存储器位置遵循规则模式的数据值的访问序列的发生。 在检测到常规访问检测电路的这种访问序列的发生时，高速缓存使用的用于确定存储数据值的所选高速缓存行的分配策略被改变，目的是增加当 由缓存输出的被驱逐的数据值随后被写入存储器件，相关联的存储器位置驻留在已经激活的存储器位置块中。 因此，通过检测常规访问模式，并且在检测到这种模式时改变分配策略，这使得能够在存储器件内重新使用已激活的块，从而显着提高存储器利用率，从而产生性能改善和功耗降低。
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公开(公告)号：US20090216958A1
公开(公告)日：2009-08-27
申请号：US12071505
申请日：2008-02-21
IPC分类号： G06F13/40
CPC分类号： G06F13/1668 , G06F2213/0038
摘要： A data processing system in the form of an integrated circuit 2 includes a general purpose programmable processor 4 and a hardware accelerator 6. A shared memory management unit 10 provides memory management operations on behalf of both of the processor core 4 and the hardware accelerator 6. The processor 4 and the hardware accelerator 6 share a memory system 8. A first communication channel 12 between the processor 4 and the hardware accelerator 6 communicates at least control signals therebetween. A second communication channel 14 coupling the hardware accelerator 6 and the memory system 8 allows the hardware accelerator 6 to perform its own data access operations upon the memory system 8.
摘要翻译： 集成电路2形式的数据处理系统包括通用可编程处理器4和硬件加速器6.共享存储器管理单元10代表处理器核心4和硬件加速器6两者提供存储器管理操作。 处理器4和硬件加速器6共享存储器系统8.处理器4和硬件加速器6之间的第一通信信道12至少在其间通信控制信号。 耦合硬件加速器6和存储器系统8的第二通信通道14允许硬件加速器6在存储器系统8上执行其自己的数据访问操作。
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公开(公告)号：US20090150620A1
公开(公告)日：2009-06-11
申请号：US12000005
申请日：2007-12-06
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/3879 , G06F12/0815 , G06F12/1027
摘要： A data processing apparatus 2 includes a programmable general purpose processor 10 coupled to a hardware accelerator 12. A memory system 14, 6, 8 is shared by the processor 10 and the hardware accelerator 12. Memory system monitoring circuitry 16 is responsive to one or more predetermined operations performed by the processor 10 upon the memory system 14, 6, 8 to generate a trigger to the hardware accelerator 12 for it to halt its processing operations and clean any data values held as temporary variables within registers 20 of the hardware accelerator back to the memory system 14, 6, 8.
摘要翻译： 数据处理装置2包括耦合到硬件加速器12的可编程通用处理器10.存储器系统14,6,8由处理器10和硬件加速器12共享。存储器系统监视电路16响应于一个或多个 由处理器10在存储器系统14,6,8上执行的预定操作，以产生对硬件加速器12的触发，以使其停止其处理操作，并清除作为硬件加速器的寄存器20内的临时变量所保持的任何数据值。 存储器系统14,6,8。
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