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公开(公告)号：US06169310A
公开(公告)日：2001-01-02
申请号：US09205110
申请日：1998-12-03
IPC分类号： H01L2362
CPC分类号： H01L27/0288
摘要： An ESD protection device for use with an integrated circuit that provides a low impedance resistive path between IC pads (including Vdd and Vss pads) when power to the IC is off, while assuring adequate isolation between the IC pads when the power is on. The device includes a semiconductor substrate (typically a p-type Si substrate) and at least two vertically integrated pinch resistors formed in the semiconductor substrate. Each of the vertically integrated pinch resistors is connected to a common electrical discharge line and to a pad. Each of the vertically integrated pinch resistors includes a deep well region and a first surface well region, both of the second conductivity type (typically n-type). The first surface well region circumscribes the deep well region, thereby forming a narrow channel region of the first conductivity type (e.g. p-type) therebetween. When no potential is applied to the first surface well regions (i.e. power is off), the two vertically integrated pinch resistors connected by the common electrical discharge line provide a low impedance resistive path between the pads for shunting ESD current. When a potential is applied to the first surface well region by the IC power supply (i.e. power is on), however, the width of the narrow channel region is pinched-off due to a potential-produced depletion region in the narrow channel region, thereby isolating the pads from each other. A process for the formation of the ESD protection device involves sequential formation of each of the device regions in a semiconductor substrate.
摘要翻译： 一种与集成电路一起使用的ESD保护装置，当IC通电时，在IC焊盘（包括Vdd和Vss焊盘）之间提供低阻抗阻抗路径，同时在电源打开时确保IC焊盘之间的充分隔离。 该器件包括形成在半导体衬底中的半导体衬底（通常为p型Si衬底）和至少两个垂直集成的夹持电阻器。 每个垂直集成的夹持电阻器连接到公共放电线和焊盘。 每个垂直集成的夹持电阻器包括深阱区域和第二表面阱区域，第二导电类型（通常为n型）。 第一表面阱区域围绕深阱区域，从而在其间形成第一导电类型（例如p型）的窄通道区域。 当没有电位施加到第一表面阱区域（即电源关闭）时，通过公共放电线连接的两个垂直集成的夹持电阻器在焊盘之间提供了阻抗ESD阻抗的低阻抗路径，用于分流ESD电流。 然而，当通过IC电源将电势施加到第一表面阱区域（即，电源接通）时，窄通道区域的宽度由于窄沟道区域中的潜在产生的耗尽区而被截断， 从而将焊盘彼此隔离。 用于形成ESD保护装置的方法包括在半导体衬底中顺序地形成每个器件区域。
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2.发明授权I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection 有权使用一对阱结构作为电阻延迟ESD事件的I / O电路和用于ESD保护的二极管公开(公告)号：US06184557B2
公开(公告)日：2001-02-06
申请号：US09239344
申请日：1999-01-28
IPC分类号： H01L2362
CPC分类号： H01L27/0255 , H01L27/0288
摘要： The n-channel and p-channel driver transistors of an I/O circuit are electrostatic discharge (ESD) protected by utilizing a pair of well structures that resistively delay an ESD event from reaching the driver transistors, and that form diodes that direct the ESD event to the supply rail or ground of the circuit.
摘要翻译： I / O电路的n沟道和p沟道驱动器晶体管是通过利用一对阱电阻保护的静电放电（ESD），其阻止ESD事件到达驱动器晶体管，并且形成指示ESD的二极管 事件到电路的电源轨或接地。
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公开(公告)号：US08363469B1
公开(公告)日：2013-01-29
申请号：US12698318
申请日：2010-02-02
CPC分类号： H01L27/115
摘要： A non-volatile memory cell includes NMOS programming, read, erase, and control transistors having gate electrodes connected to a storage node. The erase and control transistors have interconnected source, drain, and bulk electrodes. The cell is programmed by setting source, drain, bulk, and gate electrodes of all transistors to a positive voltage. An inhibiting voltage is applied to source, drain, and bulk electrodes of the read transistor, while setting source and drain electrodes of the programming transistor to the positive voltage and the bulk electrode of the programming transistor to the positive voltage or the inhibiting voltage. Source, drain, and bulk electrodes of the control transistor are then ramped to a negative control voltage while ramping source, drain, and bulk electrodes of the erase transistor to a negative erase voltage and then back to the positive voltage. Source, drain. bulk, and gate electrodes of the programming, erase, and control transistors are then returned to the positive voltage, while setting the source, drain, and bulk electrodes of the read transistor to the inhibiting voltage.
摘要翻译： 非易失性存储单元包括具有连接到存储节点的栅极的NMOS编程，读取，擦除和控制晶体管。 擦除和控制晶体管具有互连的源极，漏极和体电极。 通过将所有晶体管的源极，漏极，体积和栅极电极设置为正电压来对单元进行编程。 在将编程晶体管的源极和漏极电极设置为正电压和编程晶体管的体电极至正电压或抑制电压的同时，将读取晶体管的源极，漏极和体电极施加抑制电压。 然后，控制晶体管的源极，漏极和体电极斜坡到负的控制电压，同时将擦除晶体管的源极，漏极和体电极斜缓到负的擦除电压，然后返回到正的电压。 来源，流失。 然后将编程，擦除和控制晶体管的体积和栅电极返回到正电压，同时将读取晶体管的源极，漏极和体电极设置为抑制电压。
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公开(公告)号：USRE44130E1
公开(公告)日：2013-04-02
申请号：US13011649
申请日：2011-01-21
申请人： Elroy M. Lucero , Daniel J. Lucero , Hengyang (James) Lin , Andrew J. Franklin , Pavel Poplevine
发明人： Elroy M. Lucero , Daniel J. Lucero , Hengyang (James) Lin , Andrew J. Franklin , Pavel Poplevine
IPC分类号： G06F11/07
CPC分类号： G06F21/73
摘要： Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that provides a multi-bit die ID data string that is unique to the integrated circuit associated with the anti-pirate circuit. One time programmable (OTP) EPROM circuitry reads the die ID data string at wafer sort and writes the data content to nonvolatile memory. During a subsequent verification cycle, ID comparator circuitry compares the data string provided by the unique number generator to the stored contents of the nonvolatile memory. If the comparison results in a mismatch between more than a predefined number of bits, then the integrated circuit associated with the anti-pirate circuit is not enabled for operation.
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5.发明授权Anti-pirate circuit for protection against commercial integrated circuit pirates 有权反海盗电路，用于防止商业集成电路海盗公开(公告)号：US07558969B1
公开(公告)日：2009-07-07
申请号：US10383416
申请日：2003-03-06
申请人： Elroy M. Lucero , Daniel J. Lucero , Hengyang (James) Lin , Andrew J. Franklin , Pavel Poplevine
发明人： Elroy M. Lucero , Daniel J. Lucero , Hengyang (James) Lin , Andrew J. Franklin , Pavel Poplevine
IPC分类号： G06F11/07
CPC分类号： G06F21/73
摘要： Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that provides a multi-bit die ID data string that is unique to the integrated circuit associated with the anti-pirate circuit. One time programmable (OTP) EPROM circuitry reads the die ID data string at wafer sort and writes the data content to nonvolatile memory. During a subsequent verification cycle, ID comparator circuitry compares the data string provided by the unique number generator to the stored contents of the nonvolatile memory. If the comparison results in a mismatch between more than a predefined number of bits, then the integrated circuit associated with the anti-pirate circuit is not enabled for operation.
摘要翻译： 提供反盗版电路，用于防止半导体集成电路中包含的知识产权被盗。 反盗版电路包括唯一的数字发生器，其提供与反盗版电路相关联的集成电路所独有的多位芯片ID数据串。 一次可编程（OTP）EPROM电路读取晶片分类中的芯片ID数据串，并将数据内容写入非易失性存储器。 在随后的验证周期中，ID比较器电路将由唯一编号发生器提供的数据串与非易失性存储器的存储内容进行比较。 如果比较导致超过预定数量的比特之间的不匹配，则与反盗版电路相关联的集成电路不能被使能以进行操作。
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6.发明授权4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS structure 有权具有PMOS-NMOS-PMOS-NMOS结构的4晶体管非易失性存储单元公开(公告)号：US08213227B2
公开(公告)日：2012-07-03
申请号：US12751012
申请日：2010-03-31
CPC分类号： G11C16/0441 , G11C16/10
摘要： A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.
摘要翻译： 非易失性存储器（NVM）单元结构包括具有源极，漏极和体区电极的PMOS程序晶体管和连接到数据存储节点的栅电极; NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅电极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS读取晶体管和连接到数据存储节点的栅电极。
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7.发明授权Non-volatile memory cell with improved programming technique with decoupling pass gates and equalize transistors 有权具有改进的编程技术的非易失性存储单元，具有去耦合通过栅极和均衡晶体管公开(公告)号：US07656698B1
公开(公告)日：2010-02-02
申请号：US11656650
申请日：2007-01-23
IPC分类号： G11C11/00
CPC分类号： G11C14/0063 , G11C16/0441
摘要： A 4-transistor non-volatile memory (NVM) cell includes a static random access memory (SRAM) cell structure. The NVM cell utilizes a reverse Fowler-Nordheim tunneling programming technique that, in combination with the SRAM cell structure, allows an entire array to be programmed at one cycle. Equalize transistors are utilized to obtain more uniform voltage on the floating gates after an erase operation. Utilization of decoupling pas gates during a read operation results in more charge difference on floating gates of programmed and erased cells.
摘要翻译： 4晶体管非易失性存储器（NVM）单元包括静态随机存取存储器（SRAM）单元结构。 NVM单元采用反向Fowler-Nordheim隧道编程技术，其结合SRAM单元结构允许在一个周期对整个阵列进行编程。 利用均衡晶体管在擦除操作之后在浮动栅极上获得更均匀的电压。 在读取操作期间使用去耦pas门导致编程和擦除单元的浮动栅极上的更多的电荷差异。
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公开(公告)号：US06992927B1
公开(公告)日：2006-01-31
申请号：US10895710
申请日：2004-07-08
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C2216/10
摘要： An integrated nonvolatile memory circuit having a plurality of control devices. Separate devices execute distinct control, erase, write and read operations, thereby allowing each device to be individually selected and optimized for performing its respective operation.
摘要翻译： 一种具有多个控制装置的集成非易失性存储器电路。 单独的设备执行不同的控制，擦除，写入和读取操作，从而允许单独选择和优化每个设备以进行其相应的操作。
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9.发明授权公开(公告)号：US06801046B1
公开(公告)日：2004-10-05
申请号：US09670154
申请日：2000-09-26
IPC分类号： G01R31302
CPC分类号： G01R31/311 , G01R31/002
摘要： A method for non-destructively testing an IC device to determine the ESD performance. A laser beam is used to probe the diffusions of the device. The amount of light absorbed by the diffusions is determined by monitoring the degree to which light is reflected by the device. The amount of reflection is related to the ESD susceptibility of the device in that the greater the amount of reflection, the worse the ESD performance of the device.
摘要翻译： 一种用于非破坏性测试IC器件以确定ESD性能的方法。 激光束用于探测器件的扩散。 通过监测由装置反射光的程度来确定由扩散吸收的光量。 反射量与器件的ESD敏感性有关，因为反射量越大，器件的ESD性能就越差。
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