公开(公告)号：US4581672A

公开(公告)日：1986-04-08

申请号：US528018

申请日：1983-08-31

申请人： Elroy M. Lucero

发明人： Elroy M. Lucero

IPC分类号： G11C17/00 ,  G05F1/46 ,  G05F3/24 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G05F3/08

CPC分类号： G11C16/30 ,  G05F1/465 ,  G05F3/24

摘要： A circuit for regulating the internal programming voltage (Vpp) supplied to an integrated circuit memory device. The invention limits the internal programming voltage to a maximum value no greater than the field assisted breakdown voltage of on-chip transistors and/or the field transistor threshold voltage. Representatives of the several different types of transistors provided on an integrated circuit substrate are incorporated into the voltage regulating circuit. The regulator transistors are placed in the circuit in such a way that they are designed to break down first in the event of an excessive internal programming voltage (Vpp). In this way, the regulator transistors limit the voltage sent to the operating circuitry of the integrated circuit.

摘要翻译： 用于调节提供给集成电路存储器件的内部编程电压（Vpp）的电路。 本发明将内部编程电压限制在不大于片上晶体管的场辅助击穿电压和/或场晶体管阈值电压的最大值。 设置在集成电路基板上的几种不同类型的晶体管的代表被结合到电压调节电路中。 调节器晶体管以这样的方式被放置在电路中，使得它们被设计成在内部编程电压过大（Vpp）的情况下首先分解。 以这种方式，调节器晶体管限制发送到集成电路的工作电路的电压。

公开(公告)号：US4858185A

公开(公告)日：1989-08-15

申请号：US149568

申请日：1988-01-28

申请人： Vikram Kowshik ,  Elroy M. Lucero

发明人： Vikram Kowshik ,  Elroy M. Lucero

IPC分类号： G11C17/00 ,  G11C14/00 ,  G11C16/04 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  H03K3/356

CPC分类号： G11C14/00 ,  H03K3/356008

摘要： A compact, nonvolatile, zero static power, electrically alterable, bistable CMOS latch device is fabricated with single layer of polysilicon. The single polysilicon layer forms the floating gates of the nonvolatile elements of the device. The control gates are formed in the substrate by buried N+ diffusions and are separated from their respective floating gates by a thin oxide dielectric. The circuit can be designed to power-up in a preferred mode even before any programming operation has been performed on it. Thereafter, the circuit is available to be programmed to either of its two stable states. After the programming operation is completed and the circuit is latched to one of its two stable states, the fields across the thin oxide dielectrics are minimal and virtually no read disturb condition exist. Thus, the latch also offers excellent data retention characteristics.

摘要翻译： 使用单层多晶硅制造紧凑，非易失性，零静态功率，电可更改的双稳态CMOS锁存器件。 单个多晶硅层形成器件的非易失性元件的浮动栅极。 控制栅极通过掩埋的N +扩散形成在衬底中，并且通过薄氧化物电介质与它们各自的浮置栅极分离。 即使在执行任何编程操作之前，该电路也可以设计为在优选模式下上电。 此后，该电路可用于其两个稳定状态中的任何一个。 在编程操作完成并且电路被锁定到其两个稳定状态之一之后，跨越薄氧化物电介质的场是最小的并且实际上没有存在读干扰条件。 因此，锁存器还具有出色的数据保存特性。

公开(公告)号：US07928756B1

公开(公告)日：2011-04-19

申请号：US12074176

申请日：2008-02-29

申请人： Weiye Lu ,  Elroy M. Lucero ,  Thomas Tse

发明人： Weiye Lu ,  Elroy M. Lucero ,  Thomas Tse

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/00361 ,  H03K19/0016

摘要： In an I/O circuit, noise reduction and power savings are achieved by providing feedback from the output of the I/O driver to control the current through the pre-driver and thereby the current through the driver transistors after a non-zero time delay following a low to high or high to low data signal change.

摘要翻译： 在I / O电路中，通过从I / O驱动器的输出提供反馈来控制通过预驱动器的电流，从而在非零时间延迟之后通过驱动器晶体管的电流来实现噪声降低和功率节省 遵循从低到高或高到低的数据信号变化。

公开(公告)号：USRE44130E1

公开(公告)日：2013-04-02

申请号：US13011649

申请日：2011-01-21

申请人： Elroy M. Lucero ,  Daniel J. Lucero ,  Hengyang (James) Lin ,  Andrew J. Franklin ,  Pavel Poplevine

发明人： Elroy M. Lucero ,  Daniel J. Lucero ,  Hengyang (James) Lin ,  Andrew J. Franklin ,  Pavel Poplevine

IPC分类号： G06F11/07

CPC分类号： G06F21/73

摘要： Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that provides a multi-bit die ID data string that is unique to the integrated circuit associated with the anti-pirate circuit. One time programmable (OTP) EPROM circuitry reads the die ID data string at wafer sort and writes the data content to nonvolatile memory. During a subsequent verification cycle, ID comparator circuitry compares the data string provided by the unique number generator to the stored contents of the nonvolatile memory. If the comparison results in a mismatch between more than a predefined number of bits, then the integrated circuit associated with the anti-pirate circuit is not enabled for operation.

公开(公告)号：US20110286293A1

公开(公告)日：2011-11-24

申请号：US13157847

申请日：2011-06-10

申请人： Elroy M. Lucero

发明人： Elroy M. Lucero

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： H01L27/1104 ,  H01L27/0207 ,  H01L27/11 ,  Y10S257/903

摘要： A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells.

摘要翻译： 由来自静态随机存取存储器（SRAM）的逻辑状态形成唯一的数字，静态随机存取存储器（SRAM）被布置为被平衡，使得当将功率施加到SRAM时，SRAM内的存储单元呈现非随机逻辑状态。 唯一的编号是通过在向存储器单元施加功率之前对字线和位线进行接地而形成的，向存储器单元施加电力以呈现非随机逻辑状态，读取由存储器单元保持的非随机逻辑状态， 并从从存储器单元读取的逻辑状态形成唯一的数字。

公开(公告)号：US07558969B1

公开(公告)日：2009-07-07

申请号：US10383416

申请日：2003-03-06

申请人： Elroy M. Lucero ,  Daniel J. Lucero ,  Hengyang (James) Lin ,  Andrew J. Franklin ,  Pavel Poplevine

发明人： Elroy M. Lucero ,  Daniel J. Lucero ,  Hengyang (James) Lin ,  Andrew J. Franklin ,  Pavel Poplevine

IPC分类号： G06F11/07

CPC分类号： G06F21/73

摘要： Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that provides a multi-bit die ID data string that is unique to the integrated circuit associated with the anti-pirate circuit. One time programmable (OTP) EPROM circuitry reads the die ID data string at wafer sort and writes the data content to nonvolatile memory. During a subsequent verification cycle, ID comparator circuitry compares the data string provided by the unique number generator to the stored contents of the nonvolatile memory. If the comparison results in a mismatch between more than a predefined number of bits, then the integrated circuit associated with the anti-pirate circuit is not enabled for operation.

摘要翻译： 提供反盗版电路，用于防止半导体集成电路中包含的知识产权被盗。 反盗版电路包括唯一的数字发生器，其提供与反盗版电路相关联的集成电路所独有的多位芯片ID数据串。 一次可编程（OTP）EPROM电路读取晶片分类中的芯片ID数据串，并将数据内容写入非易失性存储器。 在随后的验证周期中，ID比较器电路将由唯一编号发生器提供的数据串与非易失性存储器的存储内容进行比较。 如果比较导致超过预定数量的比特之间的不匹配，则与反盗版电路相关联的集成电路不能被使能以进行操作。

公开(公告)号：US4873671A

公开(公告)日：1989-10-10

申请号：US149399

申请日：1988-01-28

申请人： Vikram Kowshik ,  Sudhakar Boddu ,  Elroy M. Lucero

发明人： Vikram Kowshik ,  Sudhakar Boddu ,  Elroy M. Lucero

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C8/04 ,  G11C16/02 ,  G11C19/00

CPC分类号： G11C7/00 ,  G11C19/00

摘要： Circuitry for serial read memory access utilizing a random starting address is disclosed. Fast read access is provided without upsetting the original data pattern stored in the memory core if the sequential read is terminated in midstream. After the last memory address is reached, the access automatically rolls over to the first address. The circuit provides both random and sequential access functions and allows the memory to be used as a shift register of variable length.

公开(公告)号：US07605619B1

公开(公告)日：2009-10-20

申请号：US11726512

申请日：2007-03-21

申请人： Weiye Lu ,  Elroy M. Lucero ,  Khusrow Kiani

发明人： Weiye Lu ,  Elroy M. Lucero ,  Khusrow Kiani

IPC分类号： H03K3/00

CPC分类号： H03K19/00315 ,  H03K2217/0018

摘要： In an I/O driver that includes a cascoded pair of PMOS driver transistors connected to a pair of cascaded NMOS driver transistors and that defines a pad output between the PMOS and NMOS driver transistors, a method of providing the CMOS I/O driver with over-voltage and back-drive protection includes providing circuitry for charging the wells of the PMOS transistors either to VDDIO during normal voltage mode by making use of the power supply, or to a common voltage during over-voltage and back-drive operation using the pad voltage.

摘要翻译： 在I / O驱动器中，包括连接到一对级联NMOS驱动器晶体管并且在PMOS和NMOS驱动器晶体管之间定义焊盘输出的PMOS驱动晶体管的并联成对的一对，提供CMOS I / O驱动器的方法 电压和背驱动保护包括提供电路，用于在正常电压模式期间通过使用电源将PMOS晶体管的阱充电至VDDIO，或者使用焊盘在过电压和后驱动操作期间将公共电压充电 电压。

公开(公告)号：US06670840B1

公开(公告)日：2003-12-30

申请号：US10205869

申请日：2002-07-26

申请人： Khusrow Kiani ,  Elroy M. Lucero

发明人： Khusrow Kiani ,  Elroy M. Lucero

IPC分类号： H03K508

CPC分类号： H03K5/08 ,  H03K19/00315

摘要： In a receiver input back-drive protection circuit and method, a pass gate is provided between the high pad voltage and the receiver input and a clamping circuit is provided, to present a reduced voltage to the receiver input during stress mode.

摘要翻译： 在接收器输入背驱动保护电路和方法中，在高焊盘电压和接收器输入之间提供传输门，并提供钳位电路，以在应力模式期间向接收器输入端提供降低的电压。

公开(公告)号：US4975878A

公开(公告)日：1990-12-04

申请号：US409958

申请日：1989-09-18

申请人： Sudhakar Boddu ,  Vikram Kowshik ,  Elroy M. Lucero

发明人： Sudhakar Boddu ,  Vikram Kowshik ,  Elroy M. Lucero

IPC分类号： G06F12/14

CPC分类号： G06F12/1441

摘要： An integrated, non-volatile memory protect register is provided for the memory array of a monolithic integrated circuit device. The memory array includes a plurality of programmable data storage registers, each having an associated address. The storage register addresses define the storage registers sequentially from an initial register in the array to a final register in the array. The memory protect register stores the address of a preselected storage register in the array. All registers in the array having addresses equal to or greater than the address of the preselected register are protected from any write operation. This address can be "locked" into the memory protect register to provide permanent data security to all protected registers.

摘要翻译： 为单片集成电路器件的存储器阵列提供集成的非易失性存储器保护寄存器。 存储器阵列包括多个可编程数据存储寄存器，每个具有相关联的地址。 存储寄存器地址从阵列中的初始寄存器顺序定义存储寄存器到阵列中的最终寄存器。 存储器保护寄存器存储阵列中预选存储寄存器的地址。 具有等于​​或大于预选寄存器地址的地址的阵列中的所有寄存器都不受任何写入操作的影响。 该地址可以“锁定”到存储器保护寄存器中，为所有受保护的寄存器提供永久的数据安全性。