公开(公告)号：US20090053888A1

公开(公告)日：2009-02-26

申请号：US12288540

申请日：2008-10-20

申请人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John C. Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara

发明人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John C. Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara

IPC分类号： H01L21/4763 ,  H01L21/31

CPC分类号： H01L21/02183 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/541 ,  C23C14/5806 ,  H01L21/02266 ,  H01L21/2855 ,  H01L21/318 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876

摘要： A method of depositing a duffusion barrier layer with overlying conductive layer or fill which lowers resistivity of a semiconductor device interconnect. The lower resistivity is achieved by inducing the formation of alpha tantalum within a tantalum-comprising barrier layer.

摘要翻译： 一种用覆盖的导电层或填充物沉积具有降低半导体器件互连电阻率的渗透阻挡层的方法。 通过诱导在含钽隔离层内形成α钽来实现较低的电阻率。

公开(公告)号：US07687909B2

公开(公告)日：2010-03-30

申请号：US11809153

申请日：2007-05-30

申请人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John C. Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara

发明人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John C. Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara

IPC分类号： H01L23/48

CPC分类号： H01L21/02183 ,  C23C14/024 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/541 ,  C23C14/5806 ,  H01L21/022 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/2855 ,  H01L21/318 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal/metal nitride barrier layer for semiconductor device applications. The barrier layer is particularly useful in contact vias where high conductivity of the via is important, and a lower resistivity barrier layer provides improved overall via conductivity.

摘要翻译： 用于半导体器件应用的金属/金属氮化物阻挡层。 阻挡层在通孔的高导电性很重要的接触孔中特别有用，并且较低电阻率的阻挡层提供改进的整体通孔导电性。

公开(公告)号：US07253109B2

公开(公告)日：2007-08-07

申请号：US11069348

申请日：2005-02-28

申请人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John C. Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara

发明人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John C. Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara

IPC分类号： H01L21/44

CPC分类号： H01L21/02183 ,  C23C14/024 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/541 ,  C23C14/5806 ,  H01L21/022 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/2855 ,  H01L21/318 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： We have discovered a method of providing a thin, approximately from about 2 Å to about 100 Å thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity, in the range of 30 μΩcm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface to form the TaN seed layer. In another embodiment of the method, a Ta film is altered on its surface to form the TaN seed layer.

摘要翻译： 我们已经发现了一种提供大约从大约2埃到大约100埃的Ta N种子层的薄的方法，其可以在钽沉积在Ta上时用于诱导形成α钽 N种子层。 此外，Ta N N种子层在30微米范围内显示低电阻率，并且可以在不存在α钽层的情况下用作低电阻率阻挡层。 在该方法的一个实施方案中，在其表面上改变TaN膜以形成Ta N N种子层。 在该方法的另一个实施方案中，在其表面上改变Ta膜以形成Ta N N种子层。

公开(公告)号：US20090269922A1

公开(公告)日：2009-10-29

申请号：US12459091

申请日：2009-06-25

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of the metal seed layer on the wafer via plasma deposition at a sufficient ratio of wafer substrate bias to DC source power that bottom coverage is achieved while resputtering of surfaces of the recessed device features is inhibited. The method also comprises depositing a second portion of the metal seed layer at a ration of substrate RF bias to DC source power such that resputtering is not inhibited.

摘要翻译： 我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。 该方法包括通过等离子体沉积将金属种子层的第一部分以足够的晶片衬底偏压比与DC源功率沉积在晶片上，达到底部覆盖范围，同时抑制凹陷器件特征的表面的再溅射。 该方法还包括以基板RF偏压的比例将金属种子层的第二部分沉积到DC源功率，使得不会抑制再溅射。

公开(公告)号：US09390970B2

公开(公告)日：2016-07-12

申请号：US11733671

申请日：2007-04-10

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/768 ,  C23C14/04 ,  C23C14/16 ,  H01L21/285

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。第一保护层 的材料通过传统的溅射或离子沉积溅射沉积在衬底表面上，结合足够低的衬底偏压，其中施加了该层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

公开(公告)号：US20100255678A1

公开(公告)日：2010-10-07

申请号：US12802701

申请日：2010-06-11

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of a copper seed layer on a wafer substrate without excessive build-up on the openings of each of the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. The method also comprises depositing a second portion of the metal seed layer while redistributing at least a portion of the bottom coverage material to the sidewalls of each recessed device feature, to provide a uniform seed layer coverage over the interior surface of the recessed device features.

摘要翻译： 我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。 该方法包括在晶片衬底上沉积铜晶种层的第一部分，而不会在多个凹陷元件特征中的每一个的开口上过多地累积，同时获得底部覆盖而无需基本上溅射底面。 该方法还包括沉积金属种子层的第二部分，同时将底部覆盖材料的至少一部分重新分配到每个凹陷装置特征的侧壁，以在凹陷装置特征的内表面上提供均匀的种子层覆盖。

公开(公告)号：US06758947B2

公开(公告)日：2004-07-06

申请号：US09886439

申请日：2001-06-20

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： C23C1400

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻的材料层的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。 使用传统的溅射或离子沉积溅射将第一保护层材料沉积在衬底表面上，结合足够低的衬底偏压，使得施加层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

公开(公告)号：US08158511B2

公开(公告)日：2012-04-17

申请号：US13068821

申请日：2011-05-20

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： A method of depositing a metal seed layer with underlying barrier layer on a wafer substrate comprising a plurality of recessed device features. A first portion of the barrier layer is deposited on the wafer substrate without excessive build-up of barrier layer material on the openings to the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. Subsequently, a metal seed layer is deposited using the same techniques used to deposit the barrier layer, to avoid excessive build up of metal seed layer material on the openings to the features, with minimal sputtering of the barrier layer surface.

摘要翻译： 一种在晶片衬底上沉积具有下层阻挡层的金属种子层的方法，包括多个凹陷的器件特征。 阻挡层的第一部分沉积在晶片衬底上，而不会在与多个凹陷器件特征的开口上过多地形成阻挡层材料，同时获得底部覆盖而无需基本上溅射底部表面。 随后，使用与沉积阻挡层相同的技术沉积金属种子层，以避免金属种子层材料在具有特征的开口上的过度积累，同时阻挡层表面的溅射最少。

公开(公告)号：US07989343B2

公开(公告)日：2011-08-02

申请号：US12802701

申请日：2010-06-11

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of a copper seed layer on a wafer substrate without excessive build-up on the openings of each of the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. The method also comprises depositing a second portion of the metal seed layer while redistributing at least a portion of the bottom coverage material to the sidewalls of each recessed device feature, to provide a uniform seed layer coverage over the interior surface of the recessed device features.

摘要翻译： 我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。 该方法包括在晶片衬底上沉积铜晶种层的第一部分，而不会在多个凹陷元件特征中的每一个的开口上过多地累积，同时获得底部覆盖而无需基本上溅射底面。 该方法还包括沉积金属种子层的第二部分，同时将底部覆盖材料的至少一部分重新分配到每个凹陷装置特征的侧壁，以在凹陷装置特征的内表面上提供均匀的种子层覆盖。

公开(公告)号：US20080166869A1

公开(公告)日：2008-07-10

申请号：US12075355

申请日：2008-03-10

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： A method of applying a sculptured copper seed layer on a semiconductor feature surface using ion deposition sputtering. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material.

摘要翻译： 使用离子沉积溅射在半导体特征表面上施加雕刻铜种子层的方法。 使用传统的溅射或离子沉积溅射将第一保护层材料沉积在衬底表面上，结合足够低的衬底偏压，使得施加层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。