Apparatus and method for store address for store address prefetch and line locking
    1.
    发明申请
    Apparatus and method for store address for store address prefetch and line locking 有权
    用于存储地址预取和线路锁定的存储地址的装置和方法

    公开(公告)号:US20050138295A1

    公开(公告)日:2005-06-23

    申请号:US10743134

    申请日:2003-12-23

    IPC分类号: G06F9/38 G06F12/00 G06F12/08

    摘要: Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.

    摘要翻译: 本发明的实施例涉及能够进行有效的高速缓冲存储器管理的存储器管理方案和装置。 该方法包括在执行时将条目写入存储缓冲器; 在退休之前确定该条目的地址是否在与商店缓冲区相关联的一级缓存中; 以及如果所述地址在所述高速缓存中处于独占或修改状态,则设置与所述存储缓冲器中的条目相关联的状态位。 该方法还包括当状态位被置位时,在退出时或之后立即将条目写入到第一级高速缓存; 并在退休时从所述商店缓冲器中分配该条目。 该方法还可以包括如果在存储缓冲器入口试图写入高速缓存之前将高速缓存线分配到高速缓冲存储器上或从高速缓冲存储器中被逐出,则重置状态位。

    Apparatus and method for store address for store address prefetch and line locking
    2.
    发明授权
    Apparatus and method for store address for store address prefetch and line locking 有权
    用于存储地址预取和线路锁定的存储地址的装置和方法

    公开(公告)号:US07130965B2

    公开(公告)日:2006-10-31

    申请号:US10743134

    申请日:2003-12-23

    IPC分类号: G06F12/00

    摘要: Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.

    摘要翻译: 本发明的实施例涉及能够进行有效的高速缓冲存储器管理的存储器管理方案和装置。 该方法包括在执行时将条目写入存储缓冲器; 在退休之前确定该条目的地址是否在与商店缓冲区相关联的一级缓存中; 以及如果所述地址在所述高速缓存中处于独占或修改状态,则设置与所述存储缓冲器中的条目相关联的状态位。 该方法还包括当状态位被置位时,在退出时或之后立即将条目写入到第一级高速缓存; 并在退休时从所述商店缓冲器中分配该条目。 该方法还可以包括如果在存储缓冲器入口试图写入高速缓存之前将高速缓存线分配到高速缓冲存储器上或者从高速缓冲存储器中被逐出,则重置状态位。

    Load mechanism
    3.
    发明申请
    Load mechanism 有权
    负载机制

    公开(公告)号:US20070156990A1

    公开(公告)日:2007-07-05

    申请号:US11323000

    申请日:2005-12-30

    IPC分类号: G06F13/00

    CPC分类号: G06F9/30043 G06F9/30032

    摘要: A method is disclosed. The method includes scheduling a load operation at least twice the size of a maximum access supported by a memory device, dividing the load operation into a plurality of separate load operation segments having a size equivalent to the maximum access supported by the memory device, and performing each of the plurality of load operation segments. A further method is disclosed where a temporary register is used to minimize the number of memory accesses to support unaligned accesses.

    摘要翻译: 公开了一种方法。 该方法包括将加载操作调度至少是由存储器件支持的最大访问大小的两倍,将加载操作划分成具有等于存储器设备支持的最大访问大小的多个单独的加载操作段,以及执行 多个加载操作段中的每一个。 公开了一种另外的方法,其中使用临时寄存器来最小化用于支持未对齐访问的存储器访问的数量。

    Load mechanism
    5.
    发明授权
    Load mechanism 有权
    负载机制

    公开(公告)号:US07457932B2

    公开(公告)日:2008-11-25

    申请号:US11323000

    申请日:2005-12-30

    IPC分类号: G06F12/00

    CPC分类号: G06F9/30043 G06F9/30032

    摘要: A method is disclosed. The method includes scheduling a load operation at least twice the size of a maximum access supported by a memory device, dividing the load operation into a plurality of separate load operation segments having a size equivalent to the maximum access supported by the memory device, and performing each of the plurality of load operation segments. A further method is disclosed where a temporary register is used to minimize the number of memory accesses to support unaligned accesses.

    摘要翻译: 公开了一种方法。 该方法包括将加载操作调度至少是由存储器件支持的最大访问大小的两倍,将加载操作划分成具有等于存储器设备支持的最大访问大小的多个单独的加载操作段,以及执行 多个加载操作段中的每一个。 公开了一种另外的方法,其中使用临时寄存器来最小化用于支持未对齐访问的存储器访问的数量。

    Stack tracker
    7.
    发明申请
    Stack tracker 审中-公开
    堆栈跟踪器

    公开(公告)号:US20070130448A1

    公开(公告)日:2007-06-07

    申请号:US11291378

    申请日:2005-12-01

    IPC分类号: G06F9/30

    摘要: Methods and apparatus to identify memory communications are described. In one embodiment, an access to a stack pointer is monitored, e.g., to maintain a stack tracker structure. The information stored in the stack tracker structure may be utilized to generate a distance value corresponding to a relative distance between a load instruction and a previous store instruction.

    摘要翻译: 描述了识别存储器通信的方法和装置。 在一个实施例中,监视对堆栈指针的访问,例如,以维持堆栈跟踪器结构。 存储在堆栈跟踪器结构中的信息可以用于产生对应于加载指令和先前存储指令之间的相对距离的距离值。

    Vector completion mask handling
    9.
    发明授权
    Vector completion mask handling 有权
    矢量完成掩码处理

    公开(公告)号:US08510536B2

    公开(公告)日:2013-08-13

    申请号:US13535685

    申请日:2012-06-28

    IPC分类号: G06F15/00 G06F15/76

    摘要: Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for execution with the operation, then the corresponding mask field within the data structure is cleared. The processor can reset if any field remains set within the data structure and can re-process the operation with operands that were not previously handled with the operation.

    摘要翻译: 提供矢量完成掩码(VCM)处理技术。 数据结构包括用于特定操作的每个操作数的掩码字段。 处理器尝试通过掩码字段在数据结构中标识的多个操作数来执行操作。 如果成功检索操作数以执行操作,则数据结构中的相应掩码字段将被清除。 如果任何字段在数据结构中保持设置,并且可以使用以前未被操作的操作数重新处理操作,则处理器可以重置。

    Vector Completion Mask Handling
    10.
    发明申请
    Vector Completion Mask Handling 有权
    矢量完成面具处理

    公开(公告)号:US20120272046A1

    公开(公告)日:2012-10-25

    申请号:US13535685

    申请日:2012-06-28

    IPC分类号: G06F9/302

    摘要: Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for execution with the operation, then the corresponding mask field within the data structure is cleared. The processor can reset if any field remains set within the data structure and can re-process the operation with operands that were not previously handled with the operation.

    摘要翻译: 提供矢量完成掩码(VCM)处理技术。 数据结构包括用于特定操作的每个操作数的掩码字段。 处理器尝试通过掩码字段在数据结构中标识的多个操作数来执行操作。 如果成功检索操作数以执行操作,则数据结构中的相应掩码字段将被清除。 如果任何字段在数据结构中保持设置,并且可以使用以前未被操作的操作数重新处理操作,则处理器可以重置。