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13 条记录 (耗时 0.023 秒)

    Resolving false dependencies of speculative load instructions
    3.
    发明授权
    Resolving false dependencies of speculative load instructions 有权
    解决投机负载指令的错误依赖

    公开(公告)号：US07603527B2

    公开(公告)日：2009-10-13

    申请号：US11541364

    申请日：2006-09-29

    申请人： Sebastien Hily ,  Zhongying Zhang ,  Per Hammarlund

    发明人： Sebastien Hily ,  Zhongying Zhang ,  Per Hammarlund

    IPC分类号： G06F13/14 ,  G06F12/08 ,  G06F9/38

    CPC分类号： G06F9/3842 ,  G06F9/3824 ,  G06F9/3834 ,  G06F12/1045

    摘要： Methods and apparatus for resolving false dependencies associated with speculatively executing load instructions in a processor core are described. In one embodiment, physical addresses of a load operation and a store operation are compared in response to a determination that the load operation may be potentially dependent on the store operation. Other embodiments are also described.

    摘要翻译： 描述了用于解决与在处理器核心中推测性地执行加载指令相关联的错误依赖性的方法和装置。 在一个实施例中，响应于负载操作可能潜在地依赖于存储操作的确定来比较加载操作和存储操作的物理地址。 还描述了其它实施例。

    Resolving false dependencies of speculative load instructions
    4.
    发明申请
    Resolving false dependencies of speculative load instructions 有权
    解决投机负载指令的错误依赖

    公开(公告)号：US20080082765A1

    公开(公告)日：2008-04-03

    申请号：US11541364

    申请日：2006-09-29

    申请人： Sebastien Hily ,  Zhongying Zhang ,  Per Hammarlund

    发明人： Sebastien Hily ,  Zhongying Zhang ,  Per Hammarlund

    IPC分类号： G06F13/00 ,  G06F12/00

    CPC分类号： G06F9/3842 ,  G06F9/3824 ,  G06F9/3834 ,  G06F12/1045

    摘要： Methods and apparatus for resolving false dependencies associated with speculatively executing load instructions in a processor core are described. In one embodiment, physical addresses of a load operation and a store operation are compared in response to a determination that the load operation may be potentially dependent on the store operation. Other embodiments are also described.

    摘要翻译： 描述了用于解决与在处理器核心中推测性地执行加载指令相关联的错误依赖性的方法和装置。 在一个实施例中，响应于负载操作可能潜在地依赖于存储操作的确定来比较加载操作和存储操作的物理地址。 还描述了其它实施例。

    Hybrid cache state and filter tracking of memory operations during a transaction
    5.
    发明授权
    Hybrid cache state and filter tracking of memory operations during a transaction 有权
    混合缓存状态和过滤器跟踪事务期间的内存操作

    公开(公告)号：US09298632B2

    公开(公告)日：2016-03-29

    申请号：US13535788

    申请日：2012-06-28

    申请人： Robert S. Chappell ,  Ravi Rajwar ,  Zhongying Zhang ,  Jason A. Bessette

    发明人： Robert S. Chappell ,  Ravi Rajwar ,  Zhongying Zhang ,  Jason A. Bessette

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F9/46

    CPC分类号： G06F12/0842 ,  G06F9/467 ,  G06F12/0897

    摘要： In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，高速缓存存储器可以存储多条高速缓存线，每条高速缓存行包括写入字段以存储写入指示符，以指示在事务性存储器的事务期间是否已经推测写入数据，以及读取集 字段以存储多个读取设置指示符，每个指示符指示对应的线程在交易已经提交之前是否已经读取数据。 与高速缓冲存储器相关联的压缩过滤器包括第一过滤器存储器，用于在事务已经提交之前存储由第一线程线程读取的高速缓存线的高速缓存行地址的表示。 描述和要求保护其他实施例。

    Method and apparatus for lock synchronization in a microprocessor system
    6.
    发明授权
    Method and apparatus for lock synchronization in a microprocessor system 有权
    用于微处理器系统中锁同步的方法和装置

    公开(公告)号：US06370625B1

    公开(公告)日：2002-04-09

    申请号：US09474698

    申请日：1999-12-29

    申请人： Douglas M. Carmean ,  Harish Kumar ,  Brent E. Lince ,  Michael D. Upton ,  Zhongying Zhang

    发明人： Douglas M. Carmean ,  Harish Kumar ,  Brent E. Lince ,  Michael D. Upton ,  Zhongying Zhang

    IPC分类号： G06F1318

    CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3842

    摘要： A method of controlling operations by one or more processors includes granting ownership of a memory location having data stored therein to a first processor and performing, in an atomic manner by the first processor, a read operation to load the data from the memory location to a register, a modify operation to modify the data in the register, and a write operation to store the data from the register to the memory location. The method also prevents other operations directed towards the data by a second processor while the read, modify, and write operations are performed by the first processor, and vice versa. Ownership of the memory location is released after performing the read, modify, and write operations so as to allow the first or second processors to perform subsequent atomic operations.

    摘要翻译： 一种控制一个或多个处理器的操作的方法包括将具有其中存储的数据的存储器位置的所有权授予第一处理器，并以原子方式由第一处理器执行读取操作，以将数据从存储器位置加载到 注册，修改操作以修改寄存器中的数据，以及写入操作，以将数据从寄存器存储到存储器位置。 当读取，修改和写入操作由第一处理器执行时，该方法还防止由第二处理器指向数据的其他操作，反之亦然。 在执行读取，修改和写入操作之后释放内存位置的所有权，以便允许第一或第二处理器执行后续的原子操作。