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1.发明授权Apparatus and method for store address for store address prefetch and line locking 有权用于存储地址预取和线路锁定的存储地址的装置和方法公开(公告)号：US07130965B2
公开(公告)日：2006-10-31
申请号：US10743134
申请日：2003-12-23
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F9/3824 , G06F12/0831
摘要： Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.
摘要翻译： 本发明的实施例涉及能够进行有效的高速缓冲存储器管理的存储器管理方案和装置。 该方法包括在执行时将条目写入存储缓冲器; 在退休之前确定该条目的地址是否在与商店缓冲区相关联的一级缓存中; 以及如果所述地址在所述高速缓存中处于独占或修改状态，则设置与所述存储缓冲器中的条目相关联的状态位。 该方法还包括当状态位被置位时，在退出时或之后立即将条目写入到第一级高速缓存; 并在退休时从所述商店缓冲器中分配该条目。 该方法还可以包括如果在存储缓冲器入口试图写入高速缓存之前将高速缓存线分配到高速缓冲存储器上或者从高速缓冲存储器中被逐出，则重置状态位。
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2.发明申请Apparatus and method for store address for store address prefetch and line locking 有权用于存储地址预取和线路锁定的存储地址的装置和方法公开(公告)号：US20050138295A1
公开(公告)日：2005-06-23
申请号：US10743134
申请日：2003-12-23
CPC分类号： G06F12/0804 , G06F9/3824 , G06F12/0831
摘要： Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.
摘要翻译： 本发明的实施例涉及能够进行有效的高速缓冲存储器管理的存储器管理方案和装置。 该方法包括在执行时将条目写入存储缓冲器; 在退休之前确定该条目的地址是否在与商店缓冲区相关联的一级缓存中; 以及如果所述地址在所述高速缓存中处于独占或修改状态，则设置与所述存储缓冲器中的条目相关联的状态位。 该方法还包括当状态位被置位时，在退出时或之后立即将条目写入到第一级高速缓存; 并在退休时从所述商店缓冲器中分配该条目。 该方法还可以包括如果在存储缓冲器入口试图写入高速缓存之前将高速缓存线分配到高速缓冲存储器上或从高速缓冲存储器中被逐出，则重置状态位。
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3.发明授权Method and apparatus for speculative prefetching in a multi-processor/multi-core message-passing machine 有权用于在多处理器/多核消息传递机器中推测预取的方法和装置公开(公告)号：US07937532B2
公开(公告)日：2011-05-03
申请号：US11731280
申请日：2007-03-30
申请人： Aaron Kunze , Erik J. Johnson , Hermann Gartler
发明人： Aaron Kunze , Erik J. Johnson , Hermann Gartler
IPC分类号： G06F13/00
CPC分类号： G06F9/3885 , G06F9/3828 , G06F9/383
摘要： In some embodiments, the invention involves a novel combination of techniques for prefetching data and passing messages between and among cores in a multi-processor/multi-core platform. In an embodiment, a receiving core has a message queue and a message prefetcher. Incoming messages are simultaneously written to the message queue and the message prefetcher. The prefetcher speculatively fetches data referenced in the received message so that the data is available when the message is executed in the execution pipeline, or shortly thereafter. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，本发明涉及用于在多处理器/多核平台中的核之间预取数据和传递消息之间的技术的新颖组合。 在一个实施例中，接收核心具有消息队列和消息预取器。 传入消息同时写入消息队列和消息预取器。 预取器推测性地获取接收到的消息中引用的数据，以便在执行流水线中执行消息时或之后不久可以获得数据。 描述和要求保护其他实施例。
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公开(公告)号：US20070156978A1
公开(公告)日：2007-07-05
申请号：US11322756
申请日：2005-12-30
申请人： Martin Dixon , David Koufaty , Camron Rust , Hermann Gartler , Frank Binns
发明人： Martin Dixon , David Koufaty , Camron Rust , Hermann Gartler , Frank Binns
CPC分类号： G06F12/1425 , G06F12/1491
摘要： Apparatuses and methods for steering SMM code region accesses are disclosed. In one embodiment, an apparatus includes a status indicator, a base storage location, and an abort storage location. The status indicator is to indicate whether the apparatus is operating in SMM. The base storage location is to store a base address and the abort storage location is to store an abort address. The base address is to specify a first memory address region at which SMM code is to be accessed. The abort address is to specify a second memory address region to which accesses to the first memory address region are to be steered if the apparatus is not operating in SMM.
摘要翻译： 公开了用于转向SMM码区域访问的装置和方法。 在一个实施例中，装置包括状态指示符，基本存储位置和中止存储位置。 状态指示灯是指示设备是否在SMM中运行。 基本存储位置是存储基地址，并且中止存储位置是存储中止地址。 基地址是指定要访问SMM代码的第一个存储器地址区域。 中止地址是指定第二存储器地址区域，如果设备不在SMM中操作，则对第一存储器地址区域进行访问将被转向。
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公开(公告)号：US07757045B2
公开(公告)日：2010-07-13
申请号：US11374222
申请日：2006-03-13
IPC分类号： G06F12/00
CPC分类号： G06F12/123
摘要： In one embodiment, the present invention includes a method for receiving a cache access request for data present in a lower-level cache line of a lower-level cache, and sending recency information regarding the lower-level cache line to a higher-level cache. The higher-level cache may be inclusive with the lower-level cache and may update age data associated with the cache line, thus reducing the likelihood of eviction of the cache line. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于接收对存在于较低级高速缓存的较低级高速缓存行中的数据的高速缓存访问请求的方法，以及将关于下级高速缓存线的新近度信息发送到更高级高速缓存 。 较高级别的缓存可以与下级缓存一起包含，并且可以更新与高速缓存行相关联的年龄数据，从而减少高速缓存线的驱逐的可能性。 描述和要求保护其他实施例。
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公开(公告)号：US20070214321A1
公开(公告)日：2007-09-13
申请号：US11374222
申请日：2006-03-13
IPC分类号： G06F12/00
CPC分类号： G06F12/123
摘要： In one embodiment, the present invention includes a method for receiving a cache access request for data present in a lower-level cache line of a lower-level cache, and sending recency information regarding the lower-level cache line to a higher-level cache. The higher-level cache may be inclusive with the lower-level cache and may update age data associated with the cache line, thus reducing the likelihood of eviction of the cache line. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于接收对存在于较低级高速缓存的较低级高速缓存行中的数据的高速缓存访问请求的方法，以及将关于下级高速缓存线的新近度信息发送到更高级别高速缓存 。 较高级别的缓存可以与下级缓存一起包含，并且可以更新与高速缓存行相关联的年龄数据，从而减少高速缓存线的驱逐的可能性。 描述和要求保护其他实施例。
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公开(公告)号：US20050138290A1
公开(公告)日：2005-06-23
申请号：US10743142
申请日：2003-12-23
申请人： Per Hammarlund , Avinash Sodani , James Allen , Ronak Singhal , Francis McKeen , Hermann Gartler
发明人： Per Hammarlund , Avinash Sodani , James Allen , Ronak Singhal , Francis McKeen , Hermann Gartler
CPC分类号： G06F9/3824 , G06F9/3861
摘要： Embodiments of the present invention relate to selectively re-executing instructions in a computer processor based on their association with a particular cache miss.
摘要翻译： 本发明的实施例涉及在计算机处理器中基于它们与特定高速缓存未命中的关联来选择性地重新执行指令。
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8.发明申请Method and apparatus for speculative prefetching in a multi-processor/multi-core message-passing machine 有权用于在多处理器/多核消息传递机器中推测预取的方法和装置公开(公告)号：US20080244231A1
公开(公告)日：2008-10-02
申请号：US11731280
申请日：2007-03-30
申请人： Aaron Kunze , Erik J. Johnson , Hermann Gartler
发明人： Aaron Kunze , Erik J. Johnson , Hermann Gartler
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3828 , G06F9/383
摘要： In some embodiments, the invention involves a novel combination of techniques for prefetching data and passing messages between and among cores in a multi-processor/multi-core platform. In an embodiment, a receiving core has a message queue and a message prefetcher. Incoming messages are simultaneously written to the message queue and the message prefetcher. The prefetcher speculatively fetches data referenced in the received message so that the data is available when the message is executed in the execution pipeline, or shortly thereafter. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，本发明涉及用于在多处理器/多核平台中的核之间预取数据和传递消息之间的技术的新颖组合。 在一个实施例中，接收核心具有消息队列和消息预取器。 传入消息同时写入消息队列和消息预取器。 预取器推测性地获取接收到的消息中引用的数据，以便在执行流水线中执行消息时或之后不久可以获得数据。 描述和要求保护其他实施例。
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公开(公告)号：US20050144398A1
公开(公告)日：2005-06-30
申请号：US10747145
申请日：2003-12-30
申请人： Per Hammarlund , Hermann Gartler
发明人： Per Hammarlund , Hermann Gartler
CPC分类号： G06F9/383 , G06F9/3834 , G06F12/0804 , G06F12/0831 , Y02D10/13
摘要： Embodiments of the present invention relate to cache coherency. In an embodiment of the invention, a cache includes one or more cache lines. A store pipeline may retrieve a tag associated with one of the cache lines. The data associated with the cache line may not retrieved and the cache line may be updated if, based on the tag, the cache line is determined to be in a modified or exclusive state.
摘要翻译： 本发明的实施例涉及高速缓存一致性。 在本发明的实施例中，高速缓存包括一个或多个高速缓存行。 存储流水线可以检索与一个缓存行相关联的标签。 如果基于标签将高速缓存行确定为处于修改或排除状态，则可能无法检索与高速缓存行相关联的数据，并且可以更新高速缓存行。
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10.发明授权公开(公告)号：US06216184B1
公开(公告)日：2001-04-10
申请号：US08927970
申请日：1997-09-11
IPC分类号： G06F1300
CPC分类号： G06F1/185 , G06F1/181 , G06F1/184 , G06F1/186 , G06F13/409
摘要： A riser card for use in a chassis includes a body having a first end and a second end. The length of the body is adequate to simultaneously allow the first end and the second end to be proximately situated at a back and a front wall of the chassis respectively. The riser card also includes a female edge connector disposed on the body that receives a male edge connector of a motherboard.
摘要翻译： 用于底盘的转接卡包括具有第一端和第二端的主体。 身体的长度足以同时允许第一端和第二端分别位于底盘的后壁和前壁上。 转接卡还包括设置在主体上的母边缘连接器，其接收母板的公边缘连接器。
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