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公开(公告)号：US20130014075A1
公开(公告)日：2013-01-10
申请号：US13617749
申请日：2012-09-14
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/31725 , G06F17/5031 , G06F2217/84
摘要： A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.
摘要翻译： 集成电路（IC）配置的方法包括至少部分地基于给定IC设计的统计定时来确定一个或多个处置标准的步骤; 以及至少部分地基于至少一个测试结构的一个或多个测量来确定根据给定IC设计的给定IC是否满足所述一个或多个处置标准。
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公开(公告)号：US08571825B2
公开(公告)日：2013-10-29
申请号：US13617749
申请日：2012-09-14
IPC分类号： G01R31/3181 , G06F11/30
CPC分类号： G01R31/31718 , G01R31/31725 , G06F17/5031 , G06F2217/84
摘要： A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.
摘要翻译： 集成电路（IC）配置的方法包括至少部分地基于给定IC设计的统计定时来确定一个或多个处置标准的步骤; 以及至少部分地基于至少一个测试结构的一个或多个测量来确定根据给定IC设计的给定IC是否满足所述一个或多个处置标准。
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公开(公告)号：US08538715B2
公开(公告)日：2013-09-17
申请号：US12832206
申请日：2010-07-08
IPC分类号： G01R31/3181 , G06F11/30
CPC分类号： G01R31/31718 , G01R31/31725 , G06F17/5031 , G06F2217/84
摘要： A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.
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公开(公告)号：US20120010837A1
公开(公告)日：2012-01-12
申请号：US12832206
申请日：2010-07-08
CPC分类号： G01R31/31718 , G01R31/31725 , G06F17/5031 , G06F2217/84
摘要： A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.
摘要翻译： 集成电路（IC）配置的方法包括至少部分地基于给定IC设计的统计定时来确定一个或多个处置标准的步骤; 以及至少部分地基于至少一个测试结构的一个或多个测量来确定根据给定IC设计的给定IC是否满足所述一个或多个处置标准。
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公开(公告)号：US06185722B2
公开(公告)日：2001-02-06
申请号：US09037469
申请日：1998-03-10
申请人： Laura Rohwedder Darden , James John Engel , Peter Anton Habitz , William John Livingstone , Daniel Joseph Mainiero , Jeannie Harrigan Panner , Michael Timothy Trick , Paul Steven Zuchowski
发明人： Laura Rohwedder Darden , James John Engel , Peter Anton Habitz , William John Livingstone , Daniel Joseph Mainiero , Jeannie Harrigan Panner , Michael Timothy Trick , Paul Steven Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F17/5018 , G06F2217/36
摘要： A computerized tool or method that calculates the capacitance and resistance of each global wire on the chip, one wire at a time. The invention steps along a track containing a wire segment, grid point by grid point, calculating the resistance and capacitance at that point. At each grid point it searches the neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire. The method delivers capacitance and resistance values for each process condition for a grid unit length of wire, given the wire type and 3 dimensional environment of the wire segment. The capacitance and resistance at a grid point along the wire are generally determined by one table lookup for wire types based on the surrounding environment. These values are added along wire segments to deliver accurate 3 dimensional capacitances and resistances. The invention can also provide for wires and spaces of various types and widths not provided for in the tables and for calculation of net to net coupling capacitances.
摘要翻译： 一种计算机工具或方法，用于计算芯片上每根全局线的电容和电阻，一次一根线。 本发明沿着包含线段的轨道，通过网格点的网格点，计算该点处的电阻和电容。 在每个网格点，它会搜索相邻元素周围的相邻轨道，以产生电容效应或影响线的电阻。 鉴于线段的线型和三维环境，该方法为网格单元长度的线的每个工艺条件提供电容和电阻值。 沿线的网格点的电容和电阻通常由基于周围环境的电线类型的一个表查找来确定。 这些值沿线段添加以提供精确的3维电容和电阻。 本发明还可以提供在表中未提供的各种类型和宽度的电线和空间以及用于计算网络与网络耦合电容的电线和空间。
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6.发明授权Method and system for performing shapes correction of a multi-cell reticle photomask design 失效用于执行多单元掩模版光掩模设计的形状校正的方法和系统公开(公告)号：US07302673B2
公开(公告)日：2007-11-27
申请号：US11162586
申请日：2005-09-15
申请人： Peter Anton Habitz , David James Hathaway , Jerry D. Hayes , Anthony D. Polson , Tad Jeffrey Wilder
发明人： Peter Anton Habitz , David James Hathaway , Jerry D. Hayes , Anthony D. Polson , Tad Jeffrey Wilder
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.
摘要翻译： 一种多光栅掩模版设计的掩模版设计校正和电参数提取的方法。 该方法包括：选择多小区掩模版设计的小区设计的子集，小区设计子集的每个小区设计具有相应的处理形状，用于确定相应小区设计位置的小区设计子集的每个小区设计 的相应形状; 基于每个相应形状的相应单元设计位置，确定每个单元设计的所有对应形状的共同形状处理规则; 以及仅对单元设计的子集的单个单元设计执行相应形状的形状处理，以生成用于所述单元设计的子集的结果数据。 还有一种包括计算机可读程序代码的计算机可用介质，其具有适于实现掩模版设计校正和电提取的方法的算法。
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