摘要:
Efficient apparatus and method for Zadoff-Chu (“Chu”) sequence generation avoids additional processing and hardware complexity of conventional quadratic generating formula followed by Discrete Fourier Transform (DFT) with a reference signal generator that produces both a Zadoff-Chu sequence and its DFT. In the wireless communication system (e.g., Long Term Evolution (LTE) system), Chu sequences are extensively used, especially in the uplink (UL). Because of the single carrier operating mode, transmitting a Chu sequence in principle involves a succession of generating that sequence, performing a DFT operation and then an IFFT operation. Assuming that the sequence length is N, the initial sequence generation requires 2N multiplications and the DFT requires more than N log 2(N) multiplications. Given the frequent processing of Chu sequences, this would represent a complexity burden. The invention makes it possible to perform the sequence generation and DFT steps without any multiplication operation, except for possibly calculating certain initial parameters.
摘要翻译:用于Zadoff-Chu(Chu)序列生成的高效装置和方法避免了常规二次生成公式的附加处理和硬件复杂性,随后是具有产生Zadoff-Chu序列及其DFT的参考信号发生器的离散傅里叶变换(DFT)。 在无线通信系统(例如,长期演进(Long Term Evolution,LTE)系统)中,尤其在上行链路(UL)中广泛使用了Chu序列。 由于单载波操作模式,原则上发送Chu序列涉及一系列生成该序列,执行DFT操作,然后进行IFFT操作。 假设序列长度为N,则初始序列生成需要2N次乘法,并且DFT需要多于N个log 2(N)乘法。 鉴于Chu序列的频繁处理,这将代表一个复杂的负担。 除了可能计算某些初始参数之外,本发明使得可以执行没有任何乘法运算的序列生成和DFT步骤。
摘要:
Efficient apparatus and method for Zadoff-Chu (“Chu”) sequence generation avoids additional processing and hardware complexity of conventional quadratic generating formula followed by Discrete Fourier Transform (DFT) with a reference signal generator that produces both a Zadoff-Chu sequence and its DFT. In the wireless communication system (e.g., Long Term Evolution (LTE) system), Chu sequences are extensively used, especially in the uplink (UL). Because of the single carrier operating mode, transmitting a Chu sequence in principle involves a succession of generating that sequence, performing a DFT operation and then an IFFT operation. Assuming that the sequence length is N, the initial sequence generation requires 2N multiplications and the DFT requires more than N log 2(N) multiplications. Given the frequent processing of Chu sequences, this would represent a complexity burden. The invention makes it possible to perform the sequence generation and DFT steps without any multiplication operation, except for possibly calculating certain initial parameters.
摘要翻译:用于Zadoff-Chu(“Chu”)序列生成的高效装置和方法避免了传统二次生成公式的附加处理和硬件复杂性,随后是具有产生Zadoff-Chu序列及其DFT的参考信号发生器的离散傅里叶变换(DFT) 。 在无线通信系统(例如,长期演进(Long Term Evolution,LTE)系统)中,尤其在上行链路(UL)中广泛使用了Chu序列。 由于单载波操作模式,原则上发送Chu序列涉及一系列生成该序列,执行DFT操作,然后进行IFFT操作。 假设序列长度为N,则初始序列生成需要2N次乘法,并且DFT需要多于N个log 2(N)乘法。 鉴于Chu序列的频繁处理,这将代表一个复杂的负担。 除了可能计算某些初始参数之外,本发明使得可以执行没有任何乘法运算的序列生成和DFT步骤。
摘要:
Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.
摘要:
Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.
摘要:
Certain aspects of the disclosure propose a unified channel estimation algorithm that combines two or more channel estimation algorithms in a single piece of hardware or software. The proposed unified channel estimation may dynamically switch, based on one or more metrics, between different modes of operation that utilize different channel estimation algorithms.
摘要:
Certain aspects of the disclosure propose parallel channel estimation and interference cancellation in a wireless communications system. For each common reference signal tone offset, interference cancellation and channel estimation may be performed independently. The proposed channel estimation method may increase performance of a system.
摘要:
Systems and methodologies are described that facilitate ensuring contention and/or collision free memory within a turbo decoder. A Posteriori Probability (APP) Random Access Memory (RAM) can be segmented or partitioned into two or more files with an interleaving sub-group within each file. This enables parallel operation in a turbo decoder and allows a turbo decoder to access multiple files simultaneously without memory access contention.
摘要:
Systems and methodologies are described that facilitate ensuring contention and/or collision free memory within a turbo decoder. A Posteriori Probability (APP) Random Access Memory (RAM) can be segmented or partitioned into two or more files with an interleaving sub-group within each file. This enables parallel operation in a turbo decoder and allows a turbo decoder to access multiple files simultaneously without memory access contention.
摘要:
Techniques for assigning multipaths to finger processors to achieve the desired data performance and low power consumption are described. A search is initially performed to obtain a set of multipaths for a transmission from at least one base station. At least one multipath (e.g., the minimum number of multipaths) having a combined performance metric (e.g., a combined SNR) exceeding a threshold is identified. The at least one multipath is assigned to, and processed by, at least one finger processor to recover the transmission from the base station(s).
摘要:
Certain aspects of the present disclosure relate to a method for processing wireless communications. According to one aspect, a processing unit may receive a plurality of code blocks of a transport block and schedule the plurality of code blocks to be decoded in parallel with a plurality of decoders. Each decoder decodes at least one code block as an independent tasks. The processing unit further collects the decoded information bits from the plurality of decoders and forwards the collected decoded information bits for further processing. In one aspect, the processing unit includes an output agent to temporarily store the decoded information bits while waiting for all code blocks of the transport block to be decoded.