公开(公告)号：US20060285424A1

公开(公告)日：2006-12-21

申请号：US11152769

申请日：2005-06-15

申请人： Peter Gregorius ,  Martin Streibl ,  Paul Wallner ,  Thomas Rickes

发明人： Peter Gregorius ,  Martin Streibl ,  Paul Wallner ,  Thomas Rickes

IPC分类号： G11C8/00

CPC分类号： G06F13/4243 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/107

摘要： A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface circuit section. The first interface circuit section is connectable to a write data-/command and address signal bus, includes a write data-/command and address re-driver/transmitter path (which may be transparent) and does not include any clock signal synchronizing circuitry, and a main write signal path including a serial-to-parallel converting and synchronizing device to synchronize with a reference clock signal received write data-/command and address signals and delivering the parallel converted write signals to the memory core. The second interface circuit section is connectable to a read data bus and includes a transparent read data re-driver/transmitter path for transmitting and re-driving received serial read data to a succeeding semiconductor memory chip and a main read signal path for inserting the parallel-to-serial converted read data from the memory core into the received serial read data stream, synchronizing the parallel-to-serial converted read data with the reference clock signal and providing the serialized read data stream to a serial read data input terminal of a corresponding second interface circuit section of a succeeding same memory chip or to a memory controller.

摘要翻译： 在包括存储器核心，第一接口电路部分和第二接口电路部分的半导体存储器芯片中实现高速接口电路。 第一接口电路部分可连接到写数据/命令和地址信号总线，包括写数据/命令和地址重新驱动器/发射机路径（其可以是透明的）并且不包括任何时钟信号同步电路， 以及包括串行到并行转换和同步装置的主写信号路径，以与接收到的写数据/命令和地址信号的参考时钟信号同步并将并行转换的写入信号传送到存储器核。 第二接口电路部分可连接到读数据总线，并且包括用于将接收的串行读取数据发送和重新驱动到后续半导体存储器芯片的透明读取数据重新驱动器/发送器路径和用于插入并行的主读取信号路径 将串行转换的读取数据从存储器核心转换成接收到的串行读取数据流，将并行到串行转换的读取数据与参考时钟信号同步，并将串行读取数据流提供给串行读取数据输入端 相应的相同存储器芯片的相应的第二接口电路部分或存储器控制器。

公开(公告)号：US07184360B2

公开(公告)日：2007-02-27

申请号：US11152769

申请日：2005-06-15

申请人： Peter Gregorius ,  Martin Streibl ,  Paul Wallner ,  Thomas Rickes

发明人： Peter Gregorius ,  Martin Streibl ,  Paul Wallner ,  Thomas Rickes

IPC分类号： G11C8/00

CPC分类号： G06F13/4243 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/107

摘要： A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface circuit section. The first interface circuit section is connectable to a write data-/command and address signal bus, includes a write data-/command and address re-driver/transmitter path (which may be transparent) and does not include any clock signal synchronizing circuitry, and a main write signal path including a serial-to-parallel converting and synchronizing device to synchronize with a reference clock signal received write data-/command and address signals and delivering the parallel converted write signals to the memory core. The second interface circuit section is connectable to a read data bus and includes a transparent read data re-driver/transmitter path for transmitting and re-driving received serial read data to a succeeding semiconductor memory chip and a main read signal path for inserting the parallel-to-serial converted read data from the memory core into the received serial read data stream, synchronizing the parallel-to-serial converted read data with the reference clock signal and providing the serialized read data stream to a serial read data input terminal of a corresponding second interface circuit section of a succeeding same memory chip or to a memory controller.

摘要翻译： 在包括存储器核心，第一接口电路部分和第二接口电路部分的半导体存储器芯片中实现高速接口电路。 第一接口电路部分可连接到写数据/命令和地址信号总线，包括写数据/命令和地址重新驱动器/发射机路径（其可以是透明的）并且不包括任何时钟信号同步电路， 以及包括串行到并行转换和同步装置的主写信号路径，以与接收到的写数据/命令和地址信号的参考时钟信号同步并将并行转换的写入信号传送到存储器核。 第二接口电路部分可连接到读数据总线，并且包括用于将接收的串行读取数据发送和重新驱动到后续半导体存储器芯片的透明读取数据重新驱动器/发送器路径和用于插入并行的主读取信号路径 将串行转换的读取数据从存储器核心转换成接收到的串行读取数据流，将并行到串行转换的读取数据与参考时钟信号同步，并将串行读取数据流提供给串行读取数据输入端 相应的相同存储器芯片的相应的第二接口电路部分或存储器控制器。

公开(公告)号：US20070071156A1

公开(公告)日：2007-03-29

申请号：US11238331

申请日：2005-09-26

申请人： Peter Gregorius ,  Martin Streibl ,  Thomas Rickes

发明人： Peter Gregorius ,  Martin Streibl ,  Thomas Rickes

IPC分类号： H03D3/24

CPC分类号： H03L7/087 ,  H03L7/091 ,  H03L7/0994 ,  H03L7/0995 ,  H03L7/113 ,  H03L7/18

摘要： A phase locked loop having reduced inherent noise is provided. The phase locked loop comprises a controlled oscillator for outputting a periodic output signal as a result of a control signal; a feedback unit for providing at least two periodic feedback signals having a constant phase shift to each other and each depending on the output signal; a phase/frequency detector for providing difference signals each depending on a periodic input signal and at least one of the feedback signals; and a control circuit for providing the control signal to the controlled oscillator depending on the difference signals.

摘要翻译： 提供具有降低的固有噪声的锁相环。 锁相环包括受控振荡器，用于作为控制信号的结果输出周期性输出信号; 反馈单元，用于提供至少两个周期性反馈信号，所述至少两个周期性反馈信号具有彼此恒定的相移并且各自取决于输出信号 相位/频率检测器，用于根据周期性输入信号和至少一个反馈信号提供差分信号; 以及根据差分信号将控制信号提供给受控振荡器的控制电路。

公开(公告)号：US07461186B2

公开(公告)日：2008-12-02

申请号：US11346993

申请日：2006-02-03

申请人： Martin Streibl ,  Peter Gregorius ,  Ralf Schledz ,  Thomas Rickes ,  Zheng Gu

发明人： Martin Streibl ,  Peter Gregorius ,  Ralf Schledz ,  Thomas Rickes ,  Zheng Gu

IPC分类号： G06F13/38 ,  G06F11/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093

摘要： The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by the output unit.

摘要翻译： 本发明提供一种用于将数据从第一时钟域传送到第二时钟域的数据切换单元，包括：第一时钟单元，用于提供第一时钟信号; 选择器级，可操作以相对于所述第一时钟信号对输入数据流进行采样; 第二时钟单元，用于提供第二时钟信号; 与所述选择器级耦合的存储单元，其中所述存储单元具有第一多个存储元件，每个存储元件可操作以存储所述采样数据流的一位数据;输出单元，用于从 第二多个存储元件相对于第二时钟信号包括在第一多个存储元件中，其中选择器级还可操作以将采样数据流的数据位连续地写入第一多个存储元件并存储 相应的存储元件中的采样数据流的相应数据位直到它们被输出单元读出。

公开(公告)号：US20070258552A1

公开(公告)日：2007-11-08

申请号：US11742577

申请日：2007-04-30

申请人： Martin Streibl ,  Peter Gregorius ,  Thomas Rickes ,  Ralf Schledz

发明人： Martin Streibl ,  Peter Gregorius ,  Thomas Rickes ,  Ralf Schledz

IPC分类号： H04L7/00

CPC分类号： H04L7/0054 ,  G11C7/1078 ,  G11C7/1084 ,  H03L7/08 ,  H04L7/007

摘要： A data receiver has a sampling unit connected to a data signal input and configured to sample a data signal amplitude and amplify the sampled data signal amplitude to a predetermined value, a sampling clock generator unit connected to the sampling unit and configured to predetermine a sampling clock for the sampling unit, an evaluation unit connected to the sampling unit and configured to determine the time duration required by the sampling unit for amplifying the sampled data signal amplitude to the predetermined value and evaluate the time duration determined, and a control unit connected to the evaluation unit and the sampling clock generator and configured to define the sampling clock on the basis of the evaluation of the time duration determined by the evaluation unit.

摘要翻译： 数据接收机具有连接到数据信号输入端并被配置为采样数据信号振幅并将采样数据信号振幅放大到预定值的采样单元，采样时钟发生器单元连接到采样单元并被配置为预先确定采样时钟 对于采样单元，评估单元连接到采样单元并且被配置为确定采样单元需要的持续时间以将采样的数据信号幅度放大到预定值并评估所确定的持续时间，以及控制单元 评估单元和采样时钟发生器，并且被配置为基于由评估单元确定的持续时间的评估来定义采样时钟。

公开(公告)号：US20070208980A1

公开(公告)日：2007-09-06

申请号：US11343946

申请日：2006-01-30

申请人： Peter Gregorius ,  Martin Streibl ,  Thomas Rickes

发明人： Peter Gregorius ,  Martin Streibl ,  Thomas Rickes

IPC分类号： G01R31/28

CPC分类号： G06F13/4059

摘要： A method of transmitting data between different clock domains includes receiving data bits on the basis of a receiving clock, sequentially storing the data bits in a ring buffer, simultaneously transmitting a number of the stored data bits from the ring buffer on the basis of a first transmitting clock, and transmitting the stored data bits from the ring buffer on the basis of a second transmitting clock.

摘要翻译： 一种在不同时钟域之间发送数据的方法包括：基于接收时钟接收数据比特，顺序地将数据比特存储在环形缓冲器中，同时基于第一 发送时钟，并且基于第二发送时钟从所述环形缓冲器发送所存储的数据比特。

公开(公告)号：US07864907B2

公开(公告)日：2011-01-04

申请号：US11742577

申请日：2007-04-30

申请人： Martin Streibl ,  Peter Gregorius ,  Thomas Rickes ,  Ralf Schledz

发明人： Martin Streibl ,  Peter Gregorius ,  Thomas Rickes ,  Ralf Schledz

IPC分类号： H04L7/00

CPC分类号： H04L7/0054 ,  G11C7/1078 ,  G11C7/1084 ,  H03L7/08 ,  H04L7/007

摘要： A data receiver has a sampling unit connected to a data signal input and configured to sample a data signal amplitude and amplify the sampled data signal amplitude to a predetermined value, a sampling clock generator unit connected to the sampling unit and configured to predetermine a sampling clock for the sampling unit, an evaluation unit connected to the sampling unit and configured to determine the time duration required by the sampling unit for amplifying the sampled data signal amplitude to the predetermined value and evaluate the time duration determined, and a control unit connected to the evaluation unit and the sampling clock generator and configured to define the sampling clock on the basis of the evaluation of the time duration determined by the evaluation unit.

摘要翻译： 数据接收机具有连接到数据信号输入端并被配置为采样数据信号振幅并将采样数据信号振幅放大到预定值的采样单元，采样时钟发生器单元连接到采样单元并被配置为预先确定采样时钟 对于采样单元，评估单元连接到采样单元并且被配置为确定采样单元需要的持续时间以将采样的数据信号幅度放大到预定值并评估所确定的持续时间，以及控制单元 评估单元和采样时钟发生器，并且被配置为基于由评估单元确定的持续时间的评估来定义采样时钟。

公开(公告)号：US20070186124A1

公开(公告)日：2007-08-09

申请号：US11346993

申请日：2006-02-03

申请人： Martin Streibl ,  Peter Gregorius ,  Ralf Schledz ,  Thomas Rickes ,  Zheng Gu

发明人： Martin Streibl ,  Peter Gregorius ,  Ralf Schledz ,  Thomas Rickes ,  Zheng Gu

IPC分类号： G06F13/38

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093

摘要： The invention provides a data handover unit for transferring data from a first clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a frame of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by the output unit.

摘要翻译： 本发明提供了一种用于将数据从第一时钟域传送到第二时钟域的数据切换单元，包括：第一时钟单元，用于提供第一时钟信号; 选择器级，可操作以相对于所述第一时钟信号对输入数据流进行采样; 第二时钟单元，用于提供第二时钟信号; 与所述选择器级耦合的存储单元，其中所述存储单元具有第一多个存储元件，每个存储元件可操作以存储所述采样数据流的一位数据;输出单元，用于从 第二多个存储元件相对于第二时钟信号包括在第一多个存储元件中，其中选择器级还可操作以将采样数据流的数据位连续地写入第一多个存储元件并存储 相应的存储元件中的采样数据流的相应数据位直到它们被输出单元读出。

公开(公告)号：US07817766B2

公开(公告)日：2010-10-19

申请号：US11554554

申请日：2006-10-30

申请人： Peter Gregorius ,  Thomas Rickes ,  Ralf Schledz ,  Martin Streibl

发明人： Peter Gregorius ,  Thomas Rickes ,  Ralf Schledz ,  Martin Streibl

IPC分类号： H03D3/24

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： A digital control loop and a method for clock generation. A control loop includes at least one phase detector configured to detect a phase shift of a feedback signal relative to a reference clock signal and output a correction signal on the basis of the phase shift detected. At least one control loop filter is configured to output, on the basis of the correction signal, a first control signal and a second control signal, the first control signal being substantially the same as the second control signal except that oscillations are suppressed in the second control signal. At least one first phase generator is configured to output a first clock signal on the basis of the first control signal and the first phase reference signal, wherein the first clock signal is transmitted at least partially as feedback signal to the phase detector. At least one second phase generator receives the second control signal and the first phase reference signal, wherein the second phase generator is functionally substantially the same as the first phase generator and is configured to output a second clock signal on the basis of the second control signal and the first phase reference signal.

摘要翻译： 数字控制回路和时钟生成方法。 控制回路包括至少一个相位检测器，被配置为检测反馈信号相对于参考时钟信号的相移，并且基于检测到的相移输出校正信号。 至少一个控制环路滤波器被配置为基于校正信号输出第一控制信号和第二控制信号，第一控制信号基本上与第二控制信号相同，除了在第二控制信号中振荡被抑制 控制信号。 至少一个第一相位发生器被配置为基于第一控制信号和第一相位参考信号来输出第一时钟信号，其中第一时钟信号至少部分地作为反馈信号发送到相位检测器。 至少一个第二相位发生器接收第二控制信号和第一相位参考信号，其中第二相位发生器在功能上基本上与第一相位发生器相同，并且被配置为基于第二控制信号输出第二时钟信号 和第一相位参考信号。

公开(公告)号：US07693247B2

公开(公告)日：2010-04-06

申请号：US11238331

申请日：2005-09-26

申请人： Peter Gregorius ,  Martin Streibl ,  Thomas Rickes

发明人： Peter Gregorius ,  Martin Streibl ,  Thomas Rickes

IPC分类号： H03D3/24

CPC分类号： H03L7/087 ,  H03L7/091 ,  H03L7/0994 ,  H03L7/0995 ,  H03L7/113 ,  H03L7/18

摘要： A phase locked loop having reduced inherent noise is provided. The phase locked loop comprises a controlled oscillator for outputting a periodic output signal as a result of a control signal; a feedback unit for providing at least two periodic feedback signals having a constant phase shift to each other and each depending on the output signal; a phase/frequency detector for providing difference signals each depending on a periodic input signal and at least one of the feedback signals; and a control circuit for providing the control signal to the controlled oscillator depending on the difference signals.

摘要翻译： 提供具有降低的固有噪声的锁相环。 锁相环包括受控振荡器，用于作为控制信号的结果输出周期性输出信号; 反馈单元，用于提供至少两个周期性反馈信号，所述至少两个周期性反馈信号具有彼此恒定的相移，并且各自取决于输出信号; 相位/频率检测器，用于根据周期性输入信号和至少一个反馈信号提供差分信号; 以及根据差分信号将控制信号提供给受控振荡器的控制电路。