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    Single event upset hardened latch
    1.
    发明授权
    Single event upset hardened latch 有权
    单个事件镦粗硬化闩锁

    公开(公告)号：US07161404B2

    公开(公告)日：2007-01-09

    申请号：US10742436

    申请日：2003-12-19

    申请人： Peter Hazucha ,  Krishnamurthy Soumyanath

    发明人： Peter Hazucha ,  Krishnamurthy Soumyanath

    IPC分类号： H03K3/289

    CPC分类号： H03K3/356156 ,  H03K3/012 ,  H03K3/0375 ,  H03K3/356173

    摘要： A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.

    摘要翻译： 公开了一种能够提供针对单个事件扰乱（SEU）的保护的硬化锁存器。 硬化的锁存器包括第一锁存器和第二锁存器，其对第一锁存器的门的子集进行镜像。 第二锁存器插入在第一锁存器的保持器电路的反馈路径中，并且与第一锁存器的保持器电路的栅极交叉耦合。 如果连续的SEU之间的时间大于锁存器的恢复时间，则锁存器会针对单个事件扰乱和任意数量的连续的SEU进行加固。 硬化锁存器的替代实施例包括分离缓冲器输出。 该实施例能够减少错误瞬变的传播。 硬化锁存器的另一替代实施例包括米勒C缓冲器输出。 该实施例能够将错误瞬变的传播降低到使用分离缓冲器输出的硬化锁存器中可实现的电平以下。

    Single event upset hardened latch
    2.
    发明授权
    Single event upset hardened latch 失效
    单个事件镦粗硬化闩锁

    公开(公告)号：US06696873B2

    公开(公告)日：2004-02-24

    申请号：US09472000

    申请日：1999-12-23

    申请人： Peter Hazucha ,  Krishnamurthy Soumyanath

    发明人： Peter Hazucha ,  Krishnamurthy Soumyanath

    IPC分类号： H03K3289

    CPC分类号： H03K3/356156 ,  H03K3/012 ,  H03K3/0375 ,  H03K3/356173

    摘要： A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.

    摘要翻译： 公开了一种能够提供针对单个事件扰乱（SEU）的保护的硬化锁存器。 硬化的锁存器包括第一锁存器和第二锁存器，其对第一锁存器的门的子集进行镜像。 第二锁存器插入在第一锁存器的保持器电路的反馈路径中，并且与第一锁存器的保持器电路的栅极交叉耦合。 如果连续的SEU之间的时间大于锁存器的恢复时间，则锁存器会针对单个事件扰乱和任意数量的连续的SEU进行加固。 硬化锁存器的替代实施例包括分离缓冲器输出。 该实施例能够减少错误瞬变的传播。 硬化锁存器的另一替代实施例包括米勒C缓冲器输出。 该实施例能够将错误瞬变的传播降低到使用分离缓冲器输出的硬化锁存器中可实现的电平以下。

    System and Method for Controlling Resonance Frequency of Film Bulk Acoustic Resonator Devices
    5.
    发明申请
    System and Method for Controlling Resonance Frequency of Film Bulk Acoustic Resonator Devices 有权
    用于控制膜体积声谐振器器件的谐振频率的系统和方法

    公开(公告)号：US20090039981A1

    公开(公告)日：2009-02-12

    申请号：US11836538

    申请日：2007-08-09

    申请人： Hiroyuki Ito ,  Hasnain Lakdawala ,  Ashoke Ravi ,  Krishnamurthy Soumyanath

    发明人： Hiroyuki Ito ,  Hasnain Lakdawala ,  Ashoke Ravi ,  Krishnamurthy Soumyanath

    IPC分类号： H03H9/13

    CPC分类号： H03H19/004 ,  H03H9/02007 ,  H03H2009/02204

    摘要： Disclosed is a system and method for controlling a resonance frequency of a Film Bulk Acoustic Resonator (FBAR) device. The system includes at least one switching capacitor coupled to the FBAR device and a modulator. The at least one switching capacitor includes at least one capacitor and a switch configuration disposed in series with the FBAR device and the at least one capacitor, which is switch configuration capable of opening and closing connection of the at least one capacitor with the FBAR device. The modulator is coupled to the switch configuration, which generates a switching condition signal based on the manufacturing variation in the FBAR device and the environmental effects on the FBAR device. The switch configuration performs opening and closing of the connection of the at least one capacitor and the FBAR device based on the switching condition signal.

    摘要翻译： 公开了一种用于控制膜体声波谐振器（FBAR）装置的谐振频率的系统和方法。 该系统包括耦合到FBAR器件和调制器的至少一个开关电容器。 所述至少一个开关电容器包括至少一个电容器和与所述FBAR器件和所述至少一个电容器串联布置的开关配置，所述至少一个电容器是能够打开和关闭所述至少一个电容器与所述FBAR器件的连接的开关配置。 调制器耦合到开关配置，其根据FBAR器件的制造变化和对FBAR器件的环境影响产生开关条件信号。 开关配置基于开关条件信号来执行至少一个电容器和FBAR器件的连接的打开和闭合。

    Domino circuits with high performance and high noise immunity
    8.
    发明授权
    Domino circuits with high performance and high noise immunity 有权
    具有高性能和高抗噪声能力的多米诺电路

    公开(公告)号：US06204696B1

    公开(公告)日：2001-03-20

    申请号：US09158410

    申请日：1998-09-22

    申请人： Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

    发明人： Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： In some embodiments, the invention includes a domino circuit having a precharge circuit including a source follower nFET device coupled to a domino stage conductor. An evaluation path circuit is also coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provide therefrom an evaluated output signal. In other embodiments, the invention includes a domino circuit having a predischarge circuit coupled to a domino stage conductor. An evaluation path circuit includes source follower nFET devices coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provides therefrom an evaluated output signal. In still other embodiments, the invention includes a domino circuit having a precharge circuit including coupled to a domino stage conductor. An evaluation path circuit is coupled to the domino stage conductor. An output stage includes an inverter to receive a signal from the domino stage conductor and to provide an evaluated output signal on an output conductor, the output stage including a duplicate evaluation path circuit coupled to an output conductor.

    摘要翻译： 在一些实施例中，本发明包括具有预充电电路的多米诺骨牌电路，该预充电电路包括耦合到多米诺骨牌导体的源极跟随器nFET器件。 评估路径电路也耦合到多米诺骨牌导体。 迟滞输出级接收来自多米诺骨牌级导体的信号并从其提供评估的输出信号。 在其他实施例中，本发明包括具有耦合到多米诺骨牌导体的预放电电路的多米诺骨牌电路。 评估路径电路包括耦合到多米诺骨牌导体的源极跟随器nFET器件。 滞后输出级接收来自多米诺骨牌级导体的信号并从其提供评估的输出信号。 在其他实施例中，本发明包括具有预充电电路的多米诺骨牌电路，其包括耦合到多米诺骨牌导体。 评估路径电路耦合到多米诺骨牌导体。 输出级包括反相器，用于从多米诺骨架导体接收信号并在输出导体上提供评估输出信号，输出级包括耦合到输出导体的重复评估路径电路。

    Adaptively extending tunable range of frequency in a closed loop
    10.
    发明授权
    Adaptively extending tunable range of frequency in a closed loop 有权
    在闭环中自适应地扩展频率的可调范围

    公开(公告)号：US07119628B2

    公开(公告)日：2006-10-10

    申请号：US10985511

    申请日：2004-11-10

    申请人： Ashoke Ravi ,  Krishnamurthy Soumyanath

    发明人： Ashoke Ravi ,  Krishnamurthy Soumyanath

    IPC分类号： H03L7/08

    CPC分类号： H03L7/18 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/107

    摘要： A semiconductor device or a circuit includes a controllable oscillator and circuitry that senses a voltage which may control the controllable oscillator and digitally controls a gain compensation, adaptively compensating for a drop in a gain against overall loop gain within a closed loop. In one embodiment, a single supply source may be used to power the closed loop while a variable gain stage that is digitally controllable may adjust the gain in a feed-forward manner based on the drop.

    摘要翻译： 半导体器件或电路包括可控振荡器和电路，其感测可控制可控振荡器并且数字控制增益补偿的电压，自适应地补偿增益中的下降与闭环内的整体环路增益。 在一个实施例中，可以使用单个供电源为闭环供电，而可数字控制的可变增益级可以基于该下降以前馈方式调节增益。