DECENTRALIZED INFORMATION SHARING NETWORK
    4.
    发明申请

    公开(公告)号:US20190173854A1

    公开(公告)日:2019-06-06

    申请号:US16198296

    申请日:2018-11-21

    申请人: Michael Beck

    发明人: Michael Beck

    摘要: A payload data can be received. The payload data can be packaged into a first immutable secure container at a first secure system. A new block of a blockchain can be created. The new block of the block chain can be separate from the first secure system. The new block can include a proof of existence of the payload data.

    Crack stops for semiconductor devices
    5.
    发明授权
    Crack stops for semiconductor devices 有权
    半导体器件的裂纹停止

    公开(公告)号:US08309435B2

    公开(公告)日:2012-11-13

    申请号:US13160214

    申请日:2011-06-14

    IPC分类号: H01L23/544

    摘要: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

    摘要翻译: 公开了用于半导体器件,半导体器件和制造半导体器件的方法的裂纹停止。 在一个实施例中,用于半导体器件的阻挡结构包括多个基本上V形的区域。 多个基本V形区域中的每一个被设置成与多个基本V形区域中的另一个相邻。

    Crack stops for semiconductor devices
    7.
    发明授权
    Crack stops for semiconductor devices 有权
    半导体器件的裂纹停止

    公开(公告)号:US08008750B2

    公开(公告)日:2011-08-30

    申请号:US12024758

    申请日:2008-02-01

    IPC分类号: H01L23/544

    摘要: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

    摘要翻译: 公开了用于半导体器件,半导体器件和制造半导体器件的方法的裂纹停止。 在一个实施例中,用于半导体器件的阻挡结构包括多个基本上V形的区域。 多个基本V形区域中的每一个被设置成与多个基本V形区域中的另一个相邻。

    System, method and operating unit for forming mixed layers for pallets
    8.
    发明申请
    System, method and operating unit for forming mixed layers for pallets 有权
    用于形成托盘混合层的系统,方法和操作单元

    公开(公告)号:US20100228385A1

    公开(公告)日:2010-09-09

    申请号:US12660727

    申请日:2010-03-03

    IPC分类号: G06F7/00 B65G57/00 G06F3/048

    摘要: A system (1), a method and an operating unit (62) for the creation of mixed layers for pallets (81, 82, 83, 84) are disclosed. A storage (10) is provided in which at least two different pack types are stored on a plurality of pallets (81, 82, 83, 84), including a plurality of layers of homogenous packs. The packs are intermediately stored in a plurality of individual, parallel conveyors (301, 302, . . . 30N) in a homogenous state. Based on the input of a user (5) on a touch panel (62), the packs are supplied to a grouping table (50) via a supply conveyor (40) in a predetermined sequence. A controller (60) is associated with the system (1) so that, in the grouping table (50), individual different pack types are allocated to the predefined positions of the different pack types as a function of predefined positions of the different pack types in a layer pattern (14) of a layer (24) of a production pallet (12).

    摘要翻译: 公开了一种用于产生用于托盘(81,82,83,84)的混合层的方法和操作单元(62)。 提供了一种存储装置,其中至少两种不同的包装类型存储在多个包括多层均匀包装的托盘(81,82,83,84)中。 这些包装以均匀的状态中间存储在多个单独的平行输送机(301,302,...,30N)中。 基于触摸面板(62)上的用户(5)的输入,经由供给传送器(40)以预定的顺序将包提供给分组表(50)。 控制器(60)与系统(1)相关联,使得在分组表(50)中,根据不同包装类型的预定位置的函数将单独的不同包类型分配给不同包类型的预定义位置 在生产托盘(12)的层(24)的层图案(14)中。

    Method and Apparatus for Reducing Charge Trapping in High-K Dielectric Material
    9.
    发明申请
    Method and Apparatus for Reducing Charge Trapping in High-K Dielectric Material 有权
    用于降低高K电介质材料电荷捕获的方法和装置

    公开(公告)号:US20100054022A1

    公开(公告)日:2010-03-04

    申请号:US12201223

    申请日:2008-08-29

    IPC分类号: G11C11/24 G11C7/00

    摘要: In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

    摘要翻译: 在一个实施例中,集成电路包括具有多个电容器的存储器阵列,用于在初始状态下存储存储器阵列中初始状态的数据。 集成电路还包括用于偶尔反转由多个电容器存储的数据的电路,并且跟踪由多个电容器存储的数据的当前状态是否对应于初始状态。 当数据的当前状态不对应于初始状态时,电路在读取操作期间将从存储器阵列读出的数据反相。

    Metal interconnect structure and method
    10.
    发明授权
    Metal interconnect structure and method 有权
    金属互连结构和方法

    公开(公告)号:US07651942B2

    公开(公告)日:2010-01-26

    申请号:US11203883

    申请日:2005-08-15

    IPC分类号: H01L21/4763

    摘要: A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive region and the trench. A sacrificial liner to release organic residues is deposited in the via and over the upper surface of the wafer, over which an organic planarization layer is deposited. The organic planarization layer is removed with a dry plasma etch, followed by a wet clean to remove the sacrificial liner. A diffusion barrier to separate the conductive material from the dielectric layers is deposited over the dual damascene structure and over the upper surface of the wafer. A conductive structure is formed over the diffusion barrier and polished to form an even surface for further processing steps.

    摘要翻译: 一种制造半导体器件的方法,该半导体器件包括具有形成在第一介电层中的导电区域的金属互连结构和上覆的低k电介质层。 在上覆电介质层中的双镶嵌结构中形成通孔和沟槽,通孔与导电区域和沟槽对准。 用于释放有机残余物的牺牲衬垫沉积在晶片的通孔和上表面上,沉积有机平坦化层。 用干等离子体蚀刻除去有机平坦化层,然后进行湿法清洁以除去牺牲衬垫。 将导电材料与电介质层分离的扩散阻挡层沉积在双镶嵌结构上并在晶片的上表面上。 导电结构形成在扩散阻挡层上并被抛光以形成用于进一步处理步骤的均匀表面。