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公开(公告)号：US09619855B2
公开(公告)日：2017-04-11
申请号：US13976843
申请日：2011-11-18
CPC分类号： G06T1/20 , G06T15/005 , G06T15/10 , G06T2200/28 , G06T2210/52
摘要： Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.
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2.发明申请公开(公告)号：US20140306949A1
公开(公告)日：2014-10-16
申请号：US13976843
申请日：2011-11-18
CPC分类号： G06T1/20 , G06T15/005 , G06T15/10 , G06T2200/28 , G06T2210/52
摘要： Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.
摘要翻译： 描述了系统，装置和方法，包括将批量的几何对象分发到多核系统，在每个处理器核心处，对相应批次的几何对象执行顶点处理和几何设置处理，将顶点处理结果存储到所有可访问的共享存储器 的核心，并将几何设置处理结果存储在本地存储中。 然后，每个特定核心可以使用从特定核心内的本地存储器获得的几何设置结果以及至少一个其他处理器核心的本地存储来执行光栅化。
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公开(公告)号：US20150277981A1
公开(公告)日：2015-10-01
申请号：US14227692
申请日：2014-03-27
申请人： Hema C. Nalluri , Aditya Navale , Peter L. Doyle , Murali Ramadoss , Balaji Vembu , Jeffery S. Boles
发明人： Hema C. Nalluri , Aditya Navale , Peter L. Doyle , Murali Ramadoss , Balaji Vembu , Jeffery S. Boles
CPC分类号： G06F9/5038 , G06T1/20
摘要： Methods and apparatuses may prioritize the processing of high priority and low priority contexts submitted to a processing unit through separate high priority and low priority context submission ports. According to one embodiment, submission of a context to the low priority port causes contexts in progress to be preempted, whereas submission of a context to the high priority port causes contexts in progress to be paused.
摘要翻译： 方法和设备可以优先处理通过单独的高优先级和低优先级上下文提交端口提交给处理单元的高优先级和低优先权上下文。 根据一个实施例，向低优先级端口提交上下文导致正在进行的上下文被抢占，而向高优先级端口提交上下文导致正在进行的上下文被暂停。
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公开(公告)号：US07298371B2
公开(公告)日：2007-11-20
申请号：US10848018
申请日：2004-05-17
申请人： Peter L. Doyle
发明人： Peter L. Doyle
CPC分类号： G06T15/005
摘要： Similar, contiguous primitives are stored as a single primitive in zone rendering bins. A primitive packet used in the bin is allowed to vary in length and the currently open type of primitive is recorded on a per-bin basis. A special code is used to specify a variable number of subsequent indices. With this mechanism, the hardware is able to start outputting and replicating primitive commands into bin lists on the fly without requiring the buffering of the entire primitive. Given the variable nature of the primitive instruction, multiple similar/sequential primitives can be concatenated using a single primitive command header.
摘要翻译： 类似的连续原语作为单个基元存储在区域渲染区域中。 允许在箱中使用的原始包在长度上变化，并且当前打开的原语类型以每个箱为单位被记录。 特殊代码用于指定可变数量的后续索引。 利用这种机制，硬件能够在不需要缓冲整个原语的情况下开始将原始命令输出和复制到bin列表中。 给定基本指令的可变性质，可以使用单个基元命令头连接多个相似/顺序图元。
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5.发明授权Apparatus, method and system with a graphics-rendering engine having a time allocator 有权具有图形渲染引擎的装置，方法和系统具有时间分配器公开(公告)号：US07164427B2
公开(公告)日：2007-01-16
申请号：US11096343
申请日：2005-03-31
申请人： Peter L. Doyle , Aditya Sreenivas
发明人： Peter L. Doyle , Aditya Sreenivas
CPC分类号： G06F3/1431 , G06T15/005
摘要： A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A time allocator arbitrates the concurrent use of the graphics-rendering engine between each independent image being rendered.
摘要翻译： 一种同时呈现独立图像以在一个或多个显示设备上显示的方法，装置和系统。 在一个实施例中，图形呈现引擎同时呈现独立图像以在多个显示设备上显示。 时间分配器在呈现的每个独立图像之间对并行使用图形渲染引擎进行仲裁。
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公开(公告)号：US06995773B2
公开(公告)日：2006-02-07
申请号：US10861589
申请日：2004-06-03
申请人： Peter L. Doyle , Aditya Sreenivas
发明人： Peter L. Doyle , Aditya Sreenivas
IPC分类号： G09G5/36
摘要： The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.
摘要翻译： 本发明通过在分箱和渲染阶段之间提供bin存储器的自动管理来优化区域渲染期间的图形性能。 本发明的实施例提供了一种机制，通过该机制，虚拟机和渲染器自动共享物理存储器页面池，以便构建bin缓冲器并在渲染后使用它们。 这样做的方式是，可以将多个分箱的场景同时排队，除非在特殊情况下不需要软件干预。 因此消除了对区域渲染bin缓冲存储器的软件管理的需要。 用于分档和渲染的多个场景也可以排队等待，无需软件干预。
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公开(公告)号：US06954208B2
公开(公告)日：2005-10-11
申请号：US10844094
申请日：2004-05-11
申请人： Peter L. Doyle , Aditya Sreenivas
发明人： Peter L. Doyle , Aditya Sreenivas
CPC分类号： G06T1/60 , G06T15/405
摘要： A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.
摘要翻译： 一种深度写入禁止装置和方法，用于控制从区域渲染系统中的深度缓存到相应的深度缓冲区的撤离，例如深度值。 当深度写入禁止电路被使能时，防止从深度缓存（通常在渲染下一个区域期间发生）到深度缓冲区的驱逐。 特别地，一旦深度缓冲器被初始化（即清除）到场景开始处的恒定值，则不需要读取深度缓冲器。 深度缓存处理每个区域内的中间深度读取和写入。 由于在呈现场景后不需要内存驻留深度缓冲区，因此不需要写入。 因此，在每个区域呈现之后，区域的最终深度值因此可被丢弃（即，而不是写入深度缓冲区）。
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公开(公告)号：US06867779B1
公开(公告)日：2005-03-15
申请号：US09470538
申请日：1999-12-22
申请人： Peter L. Doyle , Aditya Sreenivas
发明人： Peter L. Doyle , Aditya Sreenivas
CPC分类号： G06T1/20
摘要： An image is rendered by dividing the image into chunks, rendering the chunks in one of at least two devices, and determining which of the devices renders each one of at least some of the chunks based on at least one device's progress in the rendering of other chunks.
摘要翻译： 通过将图像划分成多个块来呈现图像，将块分解成至少两个设备中的一个，并且基于至少一个设备在渲染另一个设备中的进度来确定哪个设备呈现至少一些块中的每一个 块
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公开(公告)号：US06762765B2
公开(公告)日：2004-07-13
申请号：US10039791
申请日：2001-12-31
申请人： Peter L. Doyle , Thomas A. Piazza
发明人： Peter L. Doyle , Thomas A. Piazza
IPC分类号： G06F1202
CPC分类号： G06T1/60 , G06T15/005
摘要： Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.
摘要翻译： 本发明的实施例提供一种分割顶点缓冲器，其中每个顶点的数据在平行顶点缓冲器之间分割。 第一个缓冲区包含顶点X和Y数据，而第二个并行缓冲区包含顶点数据的其余部分。 给定分割顶点缓冲区，现在允许硬件分箱引擎读取和缓存顶点屏幕X和Y数据。 特别是考虑到索引顶点参考之间通常具有高水平的时间一致性，大块顶点屏幕空间X和Y的读取和高速缓存导致硬件分档输入的存储器带宽的较低和高效利用。 因此，本发明的实施例减少了硬件分组存储器带宽需求并提高了存储器利用率。
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10.发明授权Method and apparatus for the continuous and asynchronous traversal and processing of graphics data structures 失效用于连续和异步遍历和处理图形数据结构的方法和装置
公开(公告)号：US4928247A
公开(公告)日：1990-05-22
申请号：US184108
申请日：1988-04-20
申请人： Peter L. Doyle , John P. Ellenberger , Ellis O. Jones , David C. Carver , Steven D. DiPirro , Branko J. Gerovac , William P. Armstrong , Ellen S. Gibson , Raymond E. Shapiro , Kevin C. Rushforth , William C. Roach
发明人： Peter L. Doyle , John P. Ellenberger , Ellis O. Jones , David C. Carver , Steven D. DiPirro , Branko J. Gerovac , William P. Armstrong , Ellen S. Gibson , Raymond E. Shapiro , Kevin C. Rushforth , William C. Roach
IPC分类号： G06T17/00
CPC分类号： G06T17/00
摘要： A host system executes one or more application programs which results in graphic data structures. These graphic data structures are then continuously and asynchronously traversed. Traversal requests by competing application programs are scheduled and performed so that each application views the graphics processing as its own. The traversal and ordering of traversal requests provide efficient use of resources for multiple application programs.
摘要翻译： 主机系统执行一个或多个导致图形数据结构的应用程序。 然后连续和异步地遍历这些图形数据结构。 计划和执行相互竞争的应用程序的遍历请求，以便每个应用程序将图形处理视为自己的。 遍历请求的遍历和排序为多个应用程序提供了有效的资源使用。
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