公开(公告)号：US20150277981A1

公开(公告)日：2015-10-01

申请号：US14227692

申请日：2014-03-27

申请人： Hema C. Nalluri ,  Aditya Navale ,  Peter L. Doyle ,  Murali Ramadoss ,  Balaji Vembu ,  Jeffery S. Boles

发明人： Hema C. Nalluri ,  Aditya Navale ,  Peter L. Doyle ,  Murali Ramadoss ,  Balaji Vembu ,  Jeffery S. Boles

IPC分类号： G06F9/50 ,  G06T1/20

CPC分类号： G06F9/5038 ,  G06T1/20

摘要： Methods and apparatuses may prioritize the processing of high priority and low priority contexts submitted to a processing unit through separate high priority and low priority context submission ports. According to one embodiment, submission of a context to the low priority port causes contexts in progress to be preempted, whereas submission of a context to the high priority port causes contexts in progress to be paused.

摘要翻译： 方法和设备可以优先处理通过单独的高优先级和低优先级上下文提交端口提交给处理单元的高优先级和低优先权上下文。 根据一个实施例，向低优先级端口提交上下文导致正在进行的上下文被抢占，而向高优先级端口提交上下文导致正在进行的上下文被暂停。

公开(公告)号：US09619855B2

公开(公告)日：2017-04-11

申请号：US13976843

申请日：2011-11-18

申请人： Peter L. Doyle ,  Jeffery S. Boles ,  Arthur D. Hunter Jr. ,  Altug Koker ,  Aditya Navale

发明人： Peter L. Doyle ,  Jeffery S. Boles ,  Arthur D. Hunter Jr. ,  Altug Koker ,  Aditya Navale

IPC分类号： G06T15/00 ,  G06T1/20 ,  G06T15/10

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/10 ,  G06T2200/28 ,  G06T2210/52

摘要： Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.

公开(公告)号：US20140306949A1

公开(公告)日：2014-10-16

申请号：US13976843

申请日：2011-11-18

申请人： Peter L. Doyle ,  Jeffery S. Boles ,  Arthur D. Hunter Jr. ,  Altug Koker ,  Aditya Navale

发明人： Peter L. Doyle ,  Jeffery S. Boles ,  Arthur D. Hunter Jr. ,  Altug Koker ,  Aditya Navale

IPC分类号： G06T1/20 ,  G06T15/10 ,  G06T15/00

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/10 ,  G06T2200/28 ,  G06T2210/52

摘要： Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.

摘要翻译： 描述了系统，装置和方法，包括将批量的几何对象分发到多核系统，在每个处理器核心处，对相应批次的几何对象执行顶点处理和几何设置处理，将顶点处理结果存储到所有可访问的共享存储器 的核心，并将几何设置处理结果存储在本地存储中。 然后，每个特定核心可以使用从特定核心内的本地存储器获得的几何设置结果以及至少一个其他处理器核心的本地存储来执行光栅化。

公开(公告)号：US20190244418A1

公开(公告)日：2019-08-08

申请号：US16269270

申请日：2019-02-06

申请人： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

发明人： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

IPC分类号： G06T15/80 ,  G06F9/50 ,  G06T1/20 ,  G06T5/20

CPC分类号： G06T15/80 ,  G06F9/50 ,  G06F9/5011 ,  G06T1/20 ,  G06T5/20

摘要： An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

公开(公告)号：US07280113B1

公开(公告)日：2007-10-09

申请号：US09609274

申请日：2000-06-30

申请人： Kam Leung ,  Val G. Cook ,  Peter L. Doyle ,  Wing Hang Wong

发明人： Kam Leung ,  Val G. Cook ,  Peter L. Doyle ,  Wing Hang Wong

IPC分类号： G09G5/00

CPC分类号： G06T15/04 ,  G06T11/001 ,  G06T15/005

摘要： A machine readable storage media containing executable program instructions which when executed cause a digital processing system to seta plurality of operands and operators. A plurality of texture maps are sent to a processor for texture compositing. Operands are selected for a texture operation. A first logic is used wherein if the circulation of blend stages is equal to a number of blend stages, then a color saturation is performed, and a second logic that if the circulation number of blend stages does not equal the number of blend stages then at least one operand is selected for another texture compositing operation.

摘要翻译： 一种包含可执行程序指令的机器可读存储介质，其在被执行时使数字处理系统设置多个操作数和操作符。 将多个纹理贴图发送到处理器以进行纹理合成。 为纹理操作选择操作数。 使用第一逻辑，其中如果混合阶段的循环等于混合阶段的数量，则执行颜色饱和度，以及第二逻辑，如果混合阶段的循环数量不等于混合阶段的数量，则在 为另一个纹理合成操作选择最少一个操作数。

公开(公告)号：US07173627B2

公开(公告)日：2007-02-06

申请号：US09895777

申请日：2001-06-29

申请人： Peter L. Doyle ,  Aditya Sreenivas

发明人： Peter L. Doyle ,  Aditya Sreenivas

IPC分类号： G06F15/00 ,  G06F9/46

CPC分类号： G06F9/463

摘要： A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A graphics context manager stores in a first memory area and restores from the first memory area information describing a first rendering context associated with a first independent image. The graphics context manager stores in a second memory area and restores from the second memory area information describing a second rendering context associated with a second independent image.

摘要翻译： 一种同时呈现独立图像以在一个或多个显示设备上显示的方法，装置和系统。 在一个实施例中，图形呈现引擎同时呈现独立图像以在多个显示设备上显示。 图形上下文管理器存储在第一存储器区域中，并且从第一存储器区域恢复描述与第一独立图像相关联的第一渲染上下文的信息。 图形上下文管理器存储在第二存储器区域中，并且从第二存储器区域恢复描述与第二独立图像相关联的第二渲染上下文的信息。

公开(公告)号：US07298371B2

公开(公告)日：2007-11-20

申请号：US10848018

申请日：2004-05-17

申请人： Peter L. Doyle

发明人： Peter L. Doyle

IPC分类号： G06T15/30 ,  G06T15/10 ,  G06T17/00

CPC分类号： G06T15/005

摘要： Similar, contiguous primitives are stored as a single primitive in zone rendering bins. A primitive packet used in the bin is allowed to vary in length and the currently open type of primitive is recorded on a per-bin basis. A special code is used to specify a variable number of subsequent indices. With this mechanism, the hardware is able to start outputting and replicating primitive commands into bin lists on the fly without requiring the buffering of the entire primitive. Given the variable nature of the primitive instruction, multiple similar/sequential primitives can be concatenated using a single primitive command header.

摘要翻译： 类似的连续原语作为单个基元存储在区域渲染区域中。 允许在箱中使用的原始包在长度上变化，并且当前打开的原语类型以每个箱为单位被记录。 特殊代码用于指定可变数量的后续索引。 利用这种机制，硬件能够在不需要缓冲整个原语的情况下开始将原始命令输出和复制到bin列表中。 给定基本指令的可变性质，可以使用单个基元命令头连接多个相似/顺序图元。

公开(公告)号：US07164427B2

公开(公告)日：2007-01-16

申请号：US11096343

申请日：2005-03-31

申请人： Peter L. Doyle ,  Aditya Sreenivas

发明人： Peter L. Doyle ,  Aditya Sreenivas

IPC分类号： G06F12/02 ,  G09G5/36

CPC分类号： G06F3/1431 ,  G06T15/005

摘要： A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A time allocator arbitrates the concurrent use of the graphics-rendering engine between each independent image being rendered.

摘要翻译： 一种同时呈现独立图像以在一个或多个显示设备上显示的方法，装置和系统。 在一个实施例中，图形呈现引擎同时呈现独立图像以在多个显示设备上显示。 时间分配器在呈现的每个独立图像之间对并行使用图形渲染引擎进行仲裁。

公开(公告)号：US06995773B2

公开(公告)日：2006-02-07

申请号：US10861589

申请日：2004-06-03

申请人： Peter L. Doyle ,  Aditya Sreenivas

发明人： Peter L. Doyle ,  Aditya Sreenivas

IPC分类号： G09G5/36

CPC分类号： G06T1/60 ,  G06T15/04

摘要： The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.

摘要翻译： 本发明通过在分箱和渲染阶段之间提供bin存储器的自动管理来优化区域渲染期间的图形性能。 本发明的实施例提供了一种机制，通过该机制，虚拟机和渲染器自动共享物理存储器页面池，以便构建bin缓冲器并在渲染后使用它们。 这样做的方式是，可以将多个分箱的场景同时排队，除非在特殊情况下不需要软件干预。 因此消除了对区域渲染bin缓冲存储器的软件管理的需要。 用于分档和渲染的多个场景也可以排队等待，无需软件干预。

公开(公告)号：US06954208B2

公开(公告)日：2005-10-11

申请号：US10844094

申请日：2004-05-11

申请人： Peter L. Doyle ,  Aditya Sreenivas

发明人： Peter L. Doyle ,  Aditya Sreenivas

IPC分类号： G06T1/60 ,  G06F13/00 ,  G06T15/40 ,  G06T17/10

CPC分类号： G06T1/60 ,  G06T15/405

摘要： A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.

摘要翻译： 一种深度写入禁止装置和方法，用于控制从区域渲染系统中的深度缓存到相应的深度缓冲区的撤离，例如深度值。 当深度写入禁止电路被使能时，防止从深度缓存（通常在渲染下一个区域期间发生）到深度缓冲区的驱逐。 特别地，一旦深度缓冲器被初始化（即清除）到场景开始处的恒定值，则不需要读取深度缓冲器。 深度缓存处理每个区域内的中间深度读取和写入。 由于在呈现场景后不需要内存驻留深度缓冲区，因此不需要写入。 因此，在每个区域呈现之后，区域的最终深度值因此可被丢弃（即，而不是写入深度缓冲区）。