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    Microcomputer system with buffer in peripheral storage control
    9.
    发明授权
    Microcomputer system with buffer in peripheral storage control 失效
    微机系统具有缓冲区外设存储控制

    公开(公告)号：US4716522A

    公开(公告)日：1987-12-29

    申请号：US473861

    申请日：1983-03-10

    申请人： Tsuneo Funabashi ,  Kazuhiko Iwasaki ,  Hideo Nakamura

    发明人： Tsuneo Funabashi ,  Kazuhiko Iwasaki ,  Hideo Nakamura

    IPC分类号： G06F3/06 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F3/0601 ,  G06F13/28 ,  G06F2003/0691

    摘要： A microcomputer system has a peripheral storage control equipped with both a circuit which is responsive to a transfer command received from an MPU to set in a counter a transfer start address, which is designated subsequent to that command. The counter to supply an address for a buffer to control transfer of data from the output of the buffer to a common bus connected between the MPU and a RAM. A circuit is provided for controlling the aforementioned counter to count up in response to a transfer acknowledge signal which is subsequently received from a direct memory access control. In order that the data in the buffer may not be transferred to the RAM but may be rewritten, the peripheral storage control is further equipped with both a circuit for setting a rewrite address also received from the MPU in the counter, which is operative to identify the address of the selected buffer, in association with a rewrite command received from the MPU, and a circuit is also provided for applying the rewrite signal to the buffer each time the rewrite data is received after the setting operation from the MPU.

    摘要翻译： 微型计算机系统具有外围存储控制，该外围存储控制装置具有响应于从MPU接收到的传送命令的电路，在计数器中设置在该命令之后指定的传送起始地址。 该计数器为缓冲器提供地址，以控制从缓冲器的输出到连接在MPU和RAM之间的公共总线的数据传输。 提供电路，用于响应于随后从直接存储器访问控制接收的传送确认信号来控制上述计数器进行计数。 为了缓冲器中的数据可能不被传送到RAM但是可以被重写，外围存储控制还配备有用于设置也从计数器中的MPU接收的重写地址的电路，其可操作地识别 还提供与从MPU接收的重写命令相关联的所选择的缓冲器的地址和电路，用于在每次在来自MPU的设置操作之后接收到重写数据时，将重写信号施加到缓冲器。

    COMPUTER PROGRAM AND COMPUTER SYSTEM FOR PRODUCING TEST FLOW
    10.
    发明申请
    COMPUTER PROGRAM AND COMPUTER SYSTEM FOR PRODUCING TEST FLOW 失效
    用于生产测试流程的计算机程序和计算机系统

    公开(公告)号：US20110131217A1

    公开(公告)日：2011-06-02

    申请号：US12958350

    申请日：2010-12-01

    申请人： Kazuhiko Iwasaki ,  Masayuki Arai ,  Kenichi Ichino

    发明人： Kazuhiko Iwasaki ,  Masayuki Arai ,  Kenichi Ichino

    IPC分类号： G06F17/30

    CPC分类号： G01R31/2846

    摘要： A program executed on a computer including storage, processing, output, and input units, the storage unit storing test-difficulty-calculation-elements-database, test-menu-database, and test-flow-database, for each test-menu-record, the program causing the processing unit to execute: calculating test-difficulty for each test-menu-record based on test-difficulty-calculation-formula by using at least one among pieces of information indicative of relationship with netlist, the number of package/test pins, expected operational clock frequency, process technology information, power consumption, and tester storage space; identifying all relationship between DFT scheme and priority, and causing the storage unit to store information indicative of the relationship between the DFT scheme and priority into the test-flow-database; and sorting the DFT scheme in an order of the priority based on the relationship between the DFT scheme and priority, causing the storage unit to store the DFT scheme as a test flow, and causing the output unit to output the test flow.

    摘要翻译： 在包括存储，处理，输出和输入单元的计算机上执行的程序，存储单元存储测试难度计算单元数据库，测试菜单数据库和测试流程数据库， 记录，使得处理单元执行的程序：基于测试难度计算公式计算每个测试菜单记录的测试难度，通过使用指示与网表的关系的信息中的至少一个，包的数量 /测试引脚，预期的工作时钟频率，工艺技术信息，功耗和测试仪存储空间; 识别DFT方案和优先级之间的所有关系，并使存储单元将指示DFT方案和优先级之间的关系的信息存储到测试流数据库中; 以及根据DFT方案和优先级之间的关系按优先顺序排列DFT方案，使存储单元将DFT方案存储为测试流程，并使输出单元输出测试流程。