公开(公告)号：US06655599B2

公开(公告)日：2003-12-02

申请号：US09847220

申请日：2001-05-02

申请人： Peter Thueringer ,  Klaus Ully ,  Peter Kompan ,  Markus Feuser ,  Torsten Kramer

发明人： Peter Thueringer ,  Klaus Ully ,  Peter Kompan ,  Markus Feuser ,  Torsten Kramer

IPC分类号： G06K1906

CPC分类号： G06K19/0723

摘要： A data carrier (4) for the contactless communication of communication information (KD) with a transmitting/receiving station (1) includes receiving circuit (7) for receiving an HF signal (HF) containing the communication information (KD) from the transmitting/receiving station (1), and processing circuit (10) for processing the received communication information (KD), and supply voltage generating circuit (13) for rectifying the received HF signal (HF) and for energizing the processing circuit (10) with a supply voltage (UV), and reset circuit (14) for resetting, when the supply voltage (UV) decreases below a reset voltage value (UR), the processing performed by the processing circuit (10), the reset circuit (14) now being adapted to interrupt the processing of the communication information (KD) by the processing circuit (10) at least partially when the supply voltage (UV) decreases below an interruption voltage value (UU), the interruption voltage value (UU) being greater than the reset voltage value (UR).

摘要翻译： 用于通信信息（KD）与发送/接收站（1）的非接触式通信的数据载体（4）包括接收电路（7），用于从发送/接收站（1）接收包含通信信息（KD）的HF信号（HF） 接收站（1）和用于处理所接收的通信信息（KD）的处理电路（10），以及用于整流所接收的HF信号（HF）的电源电压生成电路（13），以及用于使处理电路 电源电压（UV）和复位电路（14），当电源电压（UV）降低到复位电压值（UR）以下时，由处理电路（10），复位电路（14）执行的处理 适于在电源电压（UV）降低到中断电压值（UU）以下时至少部分地中断处理电路（10）对通信信息（KD）的处理，中断电压值（UU）大于 有 电压值（UR）。

公开(公告)号：US06883103B2

公开(公告)日：2005-04-19

申请号：US09867893

申请日：2001-05-30

申请人： Peter Thueringer ,  Klaus Ully ,  Markus Feuser

发明人： Peter Thueringer ,  Klaus Ully ,  Markus Feuser

IPC分类号： H04L29/00 ,  G06K7/00 ,  G06K19/07 ,  G06K19/073 ,  G06F1/26

CPC分类号： G06K7/0008 ,  Y10T307/944

摘要： A data carrier that communicates confidential data is configured to mask process-dependent power consumption by using power stored in an internal capacitor. The capacitor is initially charged to the voltage of an external power source, and then decoupled from the external power source. The capacitor provides power to an internal processor, and consequently discharges gradually. At the end of a given time interval, the capacitor is discharged to a fixed voltage, then charged to the supply voltage. In this manner the power consumed by charging of the capacitor is decoupled from the power consumed by the processor. If the capacitor drops below a threshold voltage before processing is completed, the processor is halted. To optimize the available processing time, the time interval before discharging the capacitor to the fixed voltage is dynamically adjusted to reduce the time that the processor is halted.

摘要翻译： 传送机密数据的数据载体被配置为通过使用存储在内部电容器中的功率来屏蔽与处理相关的功耗。 电容器最初被充电到外部电源的电压，然后与外部电源分离。 电容器为内部处理器供电，从而逐渐放电。 在给定时间间隔结束时，电容器放电到固定电压，然后充电到电源电压。 以这种方式，电容器的充电消耗的功率与处理器消耗的功率分离。 如果在处理完成之前电容器降到阈值以下，处理器就会停止。 为了优化可用的处理时间，动态地调整将电容器放电到固定电压之前的时间间隔，以减少处理器停止的时间。

公开(公告)号：US06801956B2

公开(公告)日：2004-10-05

申请号：US10014862

申请日：2001-11-13

申请人： Markus Feuser ,  Kurt Koenig

发明人： Markus Feuser ,  Kurt Koenig

IPC分类号： G06F300

CPC分类号： G06K19/07733 ,  G06F3/002

摘要： An arrangement with a microprocessor, particularly a microprocessor for use in a chip card is described. The arrangement includes a microprocessor which is connected to at least a USB interfaces and an ISO interface for exchanging data signals. A selection unit within the microprocessor may be configured to select between the USB and ISO interfaces, and a switching unit within the microprocessor may be configured to subsequently switch between the USB and ISO interfaces by initiating an internal reset of the microprocessor.

摘要翻译： 描述了具有微处理器，特别是用于芯片卡的微处理器的装置。 该装置包括连接至少一个USB接口的微处理器和用于交换数据信号的ISO接口。 微处理器内的选择单元可被配置为在USB和ISO接口之间进行选择，并且微处理器内的切换单元可以被配置为随后通过启动微处理器的内部复位在USB和ISO接口之间切换。

公开(公告)号：US07647506B2

公开(公告)日：2010-01-12

申请号：US10319891

申请日：2002-12-13

申请人： Markus Feuser ,  Detlef Mueller

发明人： Markus Feuser ,  Detlef Mueller

IPC分类号： G06F12/14 ,  G06F1/26 ,  G06F7/04

CPC分类号： G06F21/10

摘要： In an integrated-circuit chip having intercommunicating modular functional units of electrical circuits, wired transmission of sensitive information signals between the functional units of the electrical circuits involves generating a reference signal and coding the sensitive information signals, after being emitted by a generating functional unit in the chip, with the reference signal to disguise the sensitive information represented by the sensitive information signals. The coded sensitive information signals are decoded with the reference signal before the sensitive information signals are received by a processing functional unit in the chip. At least one signal of the reference signal and the decoded sensitive information signals are monitored, and a hacker attack is identified in response to a determination that the decoded sensitive information signal is other than a plausible signal.

摘要翻译： 在具有电路的通信模块化功能单元的集成电路芯片中，在电路的功能单元之间的敏感信息信号的有线传输涉及产生参考信号并对敏感信息信号进行编码， 该芯片具有参考信号，以掩盖由敏感信息信号表示的敏感信息。 在敏感信息信号由芯片中的处理功能单元接收之前，编码的敏感信息信号用参考信号解码。 监视参考信号和解码的敏感信息信号的至少一个信号，并且响应于确定解码的敏感信息信号不是可信号的信号来识别黑客攻击。

公开(公告)号：US07047436B2

公开(公告)日：2006-05-16

申请号：US09888461

申请日：2001-06-25

申请人： Sabine Sommer ,  Detlef Müller ,  Markus Feuser

发明人： Sabine Sommer ,  Detlef Müller ,  Markus Feuser

IPC分类号： G06F1/04

CPC分类号： H04L29/06 ,  H04L45/745

摘要： A digital microelectronic circuit comprises a clocked data-processing unit (1) and a converting unit (2) which reads in data present at the output of the data-processing unit, performs a predetermined converting operation on the data and passes on the converted data. The converting unit is realized in an asynchronous logic circuit, such that the period of time for performing the converting operation is shorter than the shortest time interval to the next change of the data present at the output of the data-processing unit. In this way, fast, serial synchronous processes can be parallelized from the point of view of the slow synchronous system in synchronous systems which are slow relative thereto by using asynchronous logics, without a further high-frequency clock system being required.

摘要翻译： 数字微电子电路包括时钟数据处理单元（1）和转换单元（2），其读取存在于数据处理单元的输出端的数据，对数据执行预定的转换操作并传递转换的数据 。 转换单元在异步逻辑电路中实现，使得用于执行转换操作的时间段短于在数据处理单元的输出处存在的数据的下一个改变的最短时间间隔。 以这种方式，从同步系统的慢同步系统的观点来看，快速的串行同步过程可以通过使用异步逻辑相对慢的同步系统进行并行化，而不需要进一步的高频时钟系统。

公开(公告)号：US20060101284A1

公开(公告)日：2006-05-11

申请号：US10537517

申请日：2003-11-19

申请人： Markus Feuser ,  Sabine Sommer

发明人： Markus Feuser ,  Sabine Sommer

IPC分类号： G06F12/14

CPC分类号： G06F12/1408

摘要： In order to further develop a data processing device, in particular an electronic memory component, comprising a plurality of access-secured sub-areas, in particular a plurality of access-secured memory areas, each having at least one assigned parameter (an, an−1, . . . , a0), in particular address, and a method of encrypting at least one parameter (an, an−1, . . . , a0 ) in particular the address, of at least one access-secured sub-area, in particular at least one access-secured memory area, of at least one data processing device, in particular at least one electronic memory component, in such a way that on the one hand the security of such devices is increased considerably and on the other hand the associated expense and technical complexity are not too great, it is proposed that the parameter (an, an−1, . . . , a0) of at least one sub-area be capable of encryption only in certain areas, i.e. in dependence on least one further sub-area (a′n, a′n−1, . . . , a′1, a′0).

摘要翻译： 为了进一步开发数据处理设备，特别是电子存储器组件，其包括多个访问安全的子区域，特别是多个访问保护的存储区域，每个存储区域具有至少一个分配的参数（_{）只能在某些区域加密 ，即依赖于至少一个另外的子区域（a'，n'，a'n-1）。 。 。 ，“1”，“0”和“0”）。}

公开(公告)号：US06320770B1

公开(公告)日：2001-11-20

申请号：US09555307

申请日：2000-05-26

申请人： Markus Feuser

发明人： Markus Feuser

IPC分类号： H02M318

CPC分类号： G06K19/0701 ,  G06F1/26 ,  G06K19/0723 ,  G06K19/073 ,  H02M3/07 ,  Y10T307/724

摘要： The present invention relates to a data processing device (100), notably a chip card, which includes an integrated circuit (10) and a power supply. The power supply includes a voltage converter (12) which converts an output current Iaus (46), powering the integrated circuit (10), into a pulsed input current Iein (44), where Vaus≦Vein.

摘要翻译： 本发明涉及包括集成电路（10）和电源的数据处理装置（100），特别是芯片卡。 电源包括电压转换器（12），其将输出电流Iaus（46）转换成脉冲输入电流Iein（44），其中Vaus <= Vein。

公开(公告)号：US07640437B2

公开(公告)日：2009-12-29

申请号：US10537517

申请日：2003-11-19

申请人： Markus Feuser ,  Sabine Sommer

发明人： Markus Feuser ,  Sabine Sommer

IPC分类号： G06F11/30 ,  G06F12/14 ,  G06F13/00

CPC分类号： G06F12/1408

摘要： An electronic memory component provides a plurality of access-secured sub-areas. Each access-secured memory sub-area has at least one assigned parameter, for example, an address. The memory encrypts the assigned parameters of the access-secured sub-areas in such a way that on the one hand the security of such devices is increased considerably and on the other hand the associated expense and technical complexity are not too great. The encryption allows access to at least one sub-area dependent on at least one further sub-area.

摘要翻译： 电子存储器组件提供多个访问安全的子区域。 每个访问保护存储器子区域具有至少一个分配的参数，例如地址。 存储器以这样的方式加密访问安全的子区域的分配的参数，一方面这样的设备的安全性显着增加，另一方面相关联的费用和技术复杂度不是太大。 加密允许访问至少一个依赖于至少一个其他子区域的子区域。

公开(公告)号：US07500110B2

公开(公告)日：2009-03-03

申请号：US10319894

申请日：2002-12-13

申请人： Adrianus Marinus Gerardus Peeters ,  Markus Feuser

发明人： Adrianus Marinus Gerardus Peeters ,  Markus Feuser

IPC分类号： G06F9/00 ,  G06F1/00 ,  G06F1/12 ,  G06F7/04 ,  G06F1/26

CPC分类号： H01L23/576 ,  G06K7/0086 ,  G06K7/0091 ,  G06K19/073 ,  H01L2924/0002 ,  H04L9/003 ,  H04L2209/08 ,  H01L2924/00

摘要： The invention relates to a method and an arrangement for increasing the security of circuits against unauthorized access, both of which can be used in particular to improve the security of cards, and particularly smart cards, against attacks in which the differential power analysis approach (DPA) is followed.DPA is a procedure that makes it possible to obtain not only purely functional details but also internal information stored in integrated circuits (e.g. smart-card controllers). The majority of non-clocked classes of circuit have the property that the performance of the circuit adjusts automatically to the voltage available.The invention adopts a new approach to enable integrated circuits and particularly non-clocked handshake logic to be protected against DPA. Advantage is taken in this case of a special property of self-timed logic by using a special power supply. As a result the processes in the self-timed logic take place in an unpredictable way and current consumption becomes affected by severe noise and DPA cannot be successfully applied.

摘要翻译： 本发明涉及一种用于增加针对未授权访问的电路的安全性的方法和装置，这两者可以特别用于提高卡的安全性，特别是针对其中差分功率分析方法（DPA）的攻击 ）。 DPA是一种使得不仅可以获得纯功能细节而且可以获得存储在集成电路（例如，智能卡控制器）中的内部信息的过程。 大多数非时钟级电路具有电路性能自动调整为可用电压的特性。 本发明采用新的方法来实现集成电路，特别是非时钟的握手逻辑以防止DPA。 在这种情况下，通过使用特殊电源，可以获得具有自定时逻辑特性的优点。 因此，自定时逻辑中的过程以不可预测的方式发生，电流消耗受到严重噪声的影响，DPA无法成功应用。

公开(公告)号：US07136892B2

公开(公告)日：2006-11-14

申请号：US10324766

申请日：2002-12-20

申请人： Markus Feuser

发明人： Markus Feuser

IPC分类号： G06F7/72

CPC分类号： G06F7/724 ,  G06F2207/7209

摘要： The invention relates to a method and multiplier for multiplying two factors from the Galois field GF (2m*p), where each of the factors can be represented as a vector of p sub-blocks with a width of m bits and p, m are positive integers greater than 1. The method and multiplier allow for a polynomial multiplication to be performed quickly and efficiently with minimum requirements in respect of for storage space. Therefore, savings can thus be achieved in respect of power consumption, crystal surface and calculation time.

摘要翻译： 本发明涉及一种用于将来自伽罗瓦域GF（2≤m* p ）的两个因子相乘的方法和乘法器，其中每个因子可以表示为具有宽度的p个子块的向量 的m位，p，m是大于1的正整数。该方法和乘法器允许以关于存储空间的最小要求快速且有效地执行多项式乘法。 因此，可以在功耗，晶面和计算时间方面实现节省。