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    Delay locked loop circuit and method
    2.
    发明申请
    Delay locked loop circuit and method 有权
    延时锁相环电路及方法

    公开(公告)号：US20080030247A1

    公开(公告)日：2008-02-07

    申请号：US11906872

    申请日：2007-10-04

    申请人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

    发明人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

    IPC分类号： H03L7/06

    CPC分类号： H03L7/08 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/10

    摘要： A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

    摘要翻译： 延迟锁定环包括初始化电路，其确保将DLL初始化为不接近延迟与控制电压特性的任一端的工作点。 初始化电路强制DLL从初始延迟开始搜索锁定点，延迟在一个方向上变化，迫使DLL跳过第一个锁定点。 初始化电路仅允许DLL改变从初始延迟到达到工作点的一个方向的电压控制延迟环的延迟。

    Delay locked loop circuit and method
    3.
    发明申请
    Delay locked loop circuit and method 有权
    延时锁相环电路及方法

    公开(公告)号：US20070120587A1

    公开(公告)日：2007-05-31

    申请号：US11699268

    申请日：2007-01-29

    申请人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

    发明人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

    IPC分类号： H03L7/06

    CPC分类号： H03L7/08 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/10

    摘要： A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

    摘要翻译： 延迟锁定环包括初始化电路，其确保将DLL初始化为不接近延迟与控制电压特性的任一端的工作点。 初始化电路强制DLL最初从初始延迟开始搜索锁定点，延迟在一个方向上变化，迫使DLL跳过第一个锁定点。 初始化电路仅允许DLL改变从初始延迟到达到工作点的一个方向的电压控制延迟环的延迟。

    Wide frequency range delay locked loop
    4.
    发明授权
    Wide frequency range delay locked loop 有权
    宽频率范围延迟锁定环路

    公开(公告)号：US08213561B2

    公开(公告)日：2012-07-03

    申请号：US13186104

    申请日：2011-07-19

    申请人： Peter Vlasenko ,  Dieter Haerle

    发明人： Peter Vlasenko ,  Dieter Haerle

    IPC分类号： H03D3/24

    CPC分类号： H03L7/081 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

    摘要： A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

    摘要翻译： 延迟锁定环路在宽频率范围内工作，具有高精度，小面积使用，低功耗和短锁定时间。 该DLL结合了模拟域和数字域。 数字域负责初始锁定和操作点稳定性，并在达到锁定后冻结。 模拟域在达到锁定后负责正常运行，并使用较小的硅面积和低功耗提供高精度。

    Delay locked loop circuit and method
    5.
    发明授权
    Delay locked loop circuit and method 有权
    延时锁相环电路及方法

    公开(公告)号：US07532050B2

    公开(公告)日：2009-05-12

    申请号：US11906872

    申请日：2007-10-04

    申请人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

    发明人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

    IPC分类号： H03L7/06

    CPC分类号： H03L7/08 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/10

    摘要： A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

    摘要翻译： 延迟锁定环包括初始化电路，其确保将DLL初始化为不接近延迟与控制电压特性的任一端的工作点。 初始化电路强制DLL最初从初始延迟开始搜索锁定点，延迟在一个方向上变化，迫使DLL跳过第一个锁定点。 初始化电路仅允许DLL改变从初始延迟到达到工作点的一个方向的电压控制延迟环的延迟。

    Delay locked loop circuit and method
    6.
    再颁专利
    Delay locked loop circuit and method 有权

    公开(公告)号：USRE43947E1

    公开(公告)日：2013-01-29

    申请号：US13105749

    申请日：2011-05-11

    申请人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

    发明人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

    IPC分类号： H03L7/06

    CPC分类号： H03L7/08 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/10

    摘要： A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

    Wide Frequency Range Delay Locked Loop
    7.
    发明申请
    Wide Frequency Range Delay Locked Loop 有权
    宽频率范围延迟锁定环

    公开(公告)号：US20110291721A1

    公开(公告)日：2011-12-01

    申请号：US13186104

    申请日：2011-07-19

    申请人： Peter Vlasenko ,  Dieter Haerle

    发明人： Peter Vlasenko ,  Dieter Haerle

    IPC分类号： H03L7/06 ,  H03K5/13

    CPC分类号： H03L7/081 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

    摘要： A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

    摘要翻译： 延迟锁定环路在宽频率范围内工作，具有高精度，小面积使用，低功耗和短锁定时间。 该DLL结合了模拟域和数字域。 数字域负责初始锁定和操作点稳定性，并在达到锁定后冻结。 模拟域在达到锁定后负责正常运行，并使用较小的硅面积和低功耗提供高精度。

    Wide frequency range delay locked loop
    8.
    发明申请
    Wide frequency range delay locked loop 有权
    宽频率范围延迟锁定环路

    公开(公告)号：US20080089459A1

    公开(公告)日：2008-04-17

    申请号：US11999162

    申请日：2007-12-04

    申请人： Peter Vlasenko ,  Dieter Haerle

    发明人： Peter Vlasenko ,  Dieter Haerle

    IPC分类号： H03D3/24

    CPC分类号： H03L7/081 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

    摘要： A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

    摘要翻译： 延迟锁定环路在宽频率范围内工作，具有高精度，小面积使用，低功耗和短锁定时间。 该DLL结合了模拟域和数字域。 数字域负责初始锁定和操作点稳定性，并在达到锁定后冻结。 模拟域在达到锁定后负责正常运行，并使用较小的硅面积和低功耗提供高精度。

    Method and apparatus for initializing a delay locked loop
    9.
    发明申请
    Method and apparatus for initializing a delay locked loop 有权
    用于初始化延迟锁定环的方法和装置

    公开(公告)号：US20060170471A1

    公开(公告)日：2006-08-03

    申请号：US11050644

    申请日：2005-02-03

    申请人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

    发明人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

    IPC分类号： H03L7/06

    CPC分类号： H03L7/08 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/10

    摘要： A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

    摘要翻译： 延迟锁定环包括初始化电路，其确保将DLL初始化为不接近延迟与控制电压特性的任一端的工作点。 初始化电路强制DLL最初从初始延迟开始搜索锁定点，延迟在一个方向上变化，迫使DLL跳过第一个锁定点。 初始化电路仅允许DLL改变从初始延迟到达到工作点的一个方向的电压控制延迟环的延迟。

    WIDE FREQUENCY RANGE DELAY LOCKED LOOP
    10.
    发明申请
    WIDE FREQUENCY RANGE DELAY LOCKED LOOP 有权
    宽频范围延迟锁定环

    公开(公告)号：US20130003483A1

    公开(公告)日：2013-01-03

    申请号：US13523406

    申请日：2012-06-14

    申请人： Peter Vlasenko ,  Dieter Haerle

    发明人： Peter Vlasenko ,  Dieter Haerle

    IPC分类号： H03L7/08 ,  G11C8/00

    CPC分类号： H03L7/081 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

    摘要： A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

    摘要翻译： 延迟锁定环路在宽频率范围内工作，具有高精度，小面积使用，低功耗和短锁定时间。 该DLL结合了模拟域和数字域。 数字域负责初始锁定和操作点稳定性，并在达到锁定后冻结。 模拟域在达到锁定后负责正常运行，并使用较小的硅面积和低功耗提供高精度。