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公开(公告)号：US09042132B2
公开(公告)日：2015-05-26
申请号：US13280885
申请日：2011-10-25
IPC分类号： H02M1/44
CPC分类号： H02M1/44
摘要： A noise suppression circuit for a power adapter is disclosed. The noise suppression circuit can reduce or eliminate adapter-induced noise that could interfere with an electronic device powered by the adapter. In one example, the noise suppression circuit can include an active circuit to detect and attenuate or cancel the induced noise. In another example, the noise suppression circuit can include an RLC circuit in parallel with the adapter choke to suppress the induced noise at the operating frequencies of the powered electronic device. In still another example, the noise suppression circuit can include a modified adapter Y capacitor connection so as to bypass the adapter choke, thereby reducing or eliminating the choke's induced noise.
摘要翻译： 公开了一种用于电源适配器的噪声抑制电路。 噪声抑制电路可以减少或消除可能干扰由适配器供电的电子设备的适配器引起的噪声。 在一个示例中，噪声抑制电路可以包括用于检测和衰减或消除感应噪声的有源电路。 在另一示例中，噪声抑制电路可以包括与适配器扼流圈并联的RLC电路，以抑制在动力电子设备的工作频率处的感应噪声。 在又一示例中，噪声抑制电路可以包括修改的适配器Y电容器连接，以绕过适配器扼流圈，从而减少或消除扼流圈的感应噪声。
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公开(公告)号：US08797282B2
公开(公告)日：2014-08-05
申请号：US12906921
申请日：2010-10-18
IPC分类号： G06F3/041
CPC分类号： G06F3/03547 , H03K17/9622 , H03K2017/9602 , H03K2217/960765
摘要： A touch sensor pattern with a secondary sensor formed substantially as part of the touch sensor pattern is provided. By forming the secondary sensor substantially as part of the touch sensor pattern, where the secondary sensor can be held at a steady state or ground during a touch scan cycle of the touch sensor, an overall thickness of the stackup at the area of the touch sensor where the secondary sensor is formed can be significantly reduced. The reduction in the thickness can allow more space for other hardware such as a device battery, for example. Moreover, grounding the secondary sensor can shield the touch sensor pattern at the area of the touch sensor pattern where the secondary sensor is formed, during a touch scan cycle.
摘要翻译： 提供了具有基本上形成为触摸传感器图案的一部分的二次传感器的触摸传感器图案。 通过形成基本上作为触摸传感器图案的一部分的二次传感器，其中辅助传感器可以在触摸传感器的触摸扫描周期期间保持在稳定状态或接地，在触摸传感器的区域处的叠层的总体厚度 可以显着地减少形成二次传感器的位置。 厚度的减小可以允许例如装置电池等其他硬件的更多空间。 此外，在触摸扫描周期期间，二次传感器的接地可以屏蔽触摸传感器图案在形成二次传感器的触摸传感器图案的区域。
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公开(公告)号：US20120092270A1
公开(公告)日：2012-04-19
申请号：US12906921
申请日：2010-10-18
IPC分类号： G06F3/041
CPC分类号： G06F3/03547 , H03K17/9622 , H03K2017/9602 , H03K2217/960765
摘要： A touch sensor pattern with a secondary sensor formed substantially as part of the touch sensor pattern is provided. By forming the secondary sensor substantially as part of the touch sensor pattern, where the secondary sensor can be held at a steady state or ground during a touch scan cycle of the touch sensor, an overall thickness of the stackup at the area of the touch sensor where the secondary sensor is formed can be significantly reduced. The reduction in the thickness can allow more space for other hardware such as a device battery, for example. Moreover, grounding the secondary sensor can shield the touch sensor pattern at the area of the touch sensor pattern where the secondary sensor is formed, during a touch scan cycle.
摘要翻译： 提供了具有基本上形成为触摸传感器图案的一部分的二次传感器的触摸传感器图案。 通过形成基本上作为触摸传感器图案的一部分的二次传感器，其中二次传感器可以在触摸传感器的触摸扫描周期期间保持在稳定状态或接地，在触摸传感器的区域处的叠层的总体厚度 可以显着地减少形成二次传感器的位置。 厚度的减小可以允许例如装置电池等其他硬件的更多空间。 此外，在触摸扫描周期期间，二次传感器的接地可以在形成二次传感器的触摸传感器图案的区域处屏蔽触摸传感器图案。
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公开(公告)号：US07315294B2
公开(公告)日：2008-01-01
申请号：US10648689
申请日：2003-08-25
申请人： Peter W. Richards
发明人： Peter W. Richards
IPC分类号： G09G3/34
CPC分类号： G09G3/346 , G09G3/2014 , G09G3/2022 , G09G2300/08 , G09G2310/0235
摘要： The present invention provides a method and apparatus of converting a stream of pixel data in space and time into a stream of bitplane data. In particular, the present invention converts the pixel data stream according to a predetermined output format. The apparatus of the present invention receives the pixel data in a “real-time” fashion, and dynamically performs predefined permutations so as to accomplish the predefined transpose operation. Alternatively, the pixel data are stored in a storage medium, and the apparatus of the present invention retrieves the pixel data and performs the predefined permutation to accomplish the predefined transpose operation. The methods and apparatus disclosed herein are especially useful for processing a high-speed stream of digital data in a flow-through manner and suitable for implementation in a hardware video pipeline. The control signal fanout and gate count of this invention are reduced compared to currently available similar techniques for converting pixel data into bitplane data.
摘要翻译： 本发明提供一种将空间和时间中的像素数据流转换成位平面数据流的方法和装置。 特别地，本发明根据预定的输出格式转换像素数据流。 本发明的装置以“实时”方式接收像素数据，并动态地执行预定义的排列，以便实现预定义的转置操作。 或者，将像素数据存储在存储介质中，并且本发明的装置检索像素数据并执行预定义的排列以完成预定义的转置操作。 本文公开的方法和装置特别适用于以流通方式处理高速数字数据流并且适合于在硬件视频流水线中实现。 与用于将像素数据转换为位平面数据的当前可用的类似技术相比，本发明的控制信号扇出和门数减少。
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公开(公告)号：US07999833B2
公开(公告)日：2011-08-16
申请号：US11963476
申请日：2007-12-21
申请人： Peter W. Richards
发明人： Peter W. Richards
CPC分类号： G09G3/346 , G09G3/2014 , G09G3/2022 , G09G2300/08 , G09G2310/0235
摘要： The present invention provides a method and apparatus of converting a stream of pixel data in space and time into a stream of bitplane data. In particular, the present invention converts the pixel data stream according to a predetermined output format. The apparatus of the present invention receives the pixel data in a “real-time” fashion, and dynamically performs predefined permutations so as to accomplish the predefined transpose operation. Alternatively, the pixel data are stored in a storage medium, and the apparatus of the present invention retrieves the pixel data and performs the predefined permutation to accomplish the predefined transpose operation. The methods and apparatus disclosed herein are especially useful for processing a high-speed stream of digital data in a flow-through manner and suitable for implementation in a hardware video pipeline. The control signal fanout and gate count of this invention are reduced compared to currently available similar techniques for converting pixel data into bitplane data.
摘要翻译： 本发明提供一种将空间和时间中的像素数据流转换成位平面数据流的方法和装置。 特别地，本发明根据预定的输出格式转换像素数据流。 本发明的装置以“实时”方式接收像素数据，并动态地执行预定义的排列，以便实现预定义的转置操作。 或者，将像素数据存储在存储介质中，并且本发明的装置检索像素数据并执行预定义的排列以完成预定义的转置操作。 本文公开的方法和装置特别适用于以流通方式处理高速数字数据流并且适合于在硬件视频流水线中实现。 与用于将像素数据转换为位平面数据的当前可用的类似技术相比，本发明的控制信号扇出和门数减少。
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公开(公告)号：US20070258312A1
公开(公告)日：2007-11-08
申请号：US11744526
申请日：2007-05-04
申请人： Peter W. Richards
发明人： Peter W. Richards
IPC分类号： G11C8/00
CPC分类号： G02B26/0841 , G09G3/2029 , G09G3/346 , G09G2300/0842 , G09G2300/0876 , G09G2310/0235 , H04N9/3105 , H04N9/3114 , H04N9/3123
摘要： Methods and apparatus for selectively updating memory cells of a memory cell array are provided. The memory cells of each row of the memory cell array are provided with a plurality of wordlines. Memory cells of the row are activated and updated by separated wordlines. In an application of display systems using memory cell arrays for controlling the pixels of the display system and pulse-width-modulation (PWM) technique for displaying grayscales, the pixels can be modulated by different PWM waveforms. The perceived dynamic-false-contouring artifacts are reduced thereby. In another application, the provision of multiple wordlines enables precise measurements of voltages maintained by memory cells of the memory cell array.
摘要翻译： 提供了选择性地更新存储单元阵列的存储单元的方法和装置。 存储单元阵列的每一行的存储单元被提供有多个字线。 该行的存储单元被分离的字线激活和更新。 在使用用于控制显示系统的像素的存储单元阵列和用于显示灰度级的脉宽调制（PWM））技术的显示系统的应用中，可以通过不同的PWM波形来调制像素。 感知到的动态假轮廓伪像由此减弱。 在另一个应用中，提供多个字线可以精确测量由存储单元阵列的存储单元维持的电压。
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公开(公告)号：US07196684B2
公开(公告)日：2007-03-27
申请号：US11349517
申请日：2006-02-06
申请人： Peter W. Richards
发明人： Peter W. Richards
IPC分类号： G09G3/36
CPC分类号： G09G3/34 , G02F1/136277 , G09G3/2018 , G09G3/346 , G09G3/3648 , G09G2300/08 , G09G2310/0235 , G09G2310/0251 , G11C11/401 , G11C11/404
摘要： A voltage storage cell circuit includes an access transistor and a storage capacitor, wherein the source of said access transistor is connected to a bitline, the gate of said access transistor is connected to a wordline, and wherein the drain of said access transistor is connected to a first plate of said storage capacitor forming a storage node, and wherein the second plate of said storage capacitor is connected to a pump signal. This arrangement allows for a novel pixel circuit design with area requirements comparable to that of a 1T1C DRAM-like pixel cell, but with the advantage of an output voltage swing of the full range allowed by the breakdown voltage of the pass transistor. A spatial light modulator such as a micromirror array can comprise such a voltage storage cell.
摘要翻译： 电压存储单元电路包括存取晶体管和存储电容器，其中所述存取晶体管的源极连接到位线，所述存取晶体管的栅极连接到字线，并且其中所述存取晶体管的漏极连接到 所述存储电容器的第一板形成存储节点，并且其中所述存储电容器的第二板连接到泵浦信号。 这种布置允许具有与1T1C类DRAM像素单元的面积要求相当的面积要求的新型像素电路设计，但是具有通过晶体管的击穿电压允许的全范围的输出电压摆幅的优点。 诸如微镜阵列的空间光调制器可以包括这种电压存储单元。
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公开(公告)号：US07027205B2
公开(公告)日：2006-04-11
申请号：US10987896
申请日：2004-11-12
申请人： Peter W. Richards
发明人： Peter W. Richards
IPC分类号： G02B26/00
CPC分类号： G09G3/34 , G02B26/0841 , G03B21/28 , G09G3/2022 , G09G3/346 , G09G2300/08 , G09G2310/02 , G09G2320/0261 , G09G2320/0266 , G11C11/408 , Y10S359/904
摘要： Methods and apparatus for selectively updating memory cells of a memory cell array are provided. The memory cells of each row of the memory cell array are provided with a plurality of wordlines. Memory cells of the row are activated and updated by separated wordlines. In an application of display systems using memory cell arrays for controlling the pixels of the display system and pulse-width-modulation (PWM) technique for displaying grayscales, the pixels can be modulated by different PWM waveforms. The perceived dynamic-false-contouring artifacts are reduced thereby. In another application, the provision of multiple wordlines enables precise measurements of voltages maintained by memory cells of the memory cell array.
摘要翻译： 提供了选择性地更新存储单元阵列的存储单元的方法和装置。 存储单元阵列的每一行的存储单元被提供有多个字线。 该行的存储单元被分离的字线激活和更新。 在使用用于控制显示系统的像素的存储单元阵列和用于显示灰度级的脉宽调制（PWM））技术的显示系统的应用中，可以通过不同的PWM波形来调制像素。 感知到的动态假轮廓伪像由此减弱。 在另一个应用中，提供多个字线可以精确测量由存储单元阵列的存储单元维持的电压。
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公开(公告)号：US07012592B2
公开(公告)日：2006-03-14
申请号：US10340162
申请日：2003-01-10
申请人： Peter W. Richards
发明人： Peter W. Richards
IPC分类号： G09G3/36
CPC分类号： G09G3/34 , G02F1/136277 , G09G3/2018 , G09G3/346 , G09G3/3648 , G09G2300/08 , G09G2310/0235 , G09G2310/0251 , G11C11/401 , G11C11/404
摘要： A voltage storage cell circuit includes an access transistor and a storage capacitor, wherein the source of said access transistor is connected to a bitline, the gate of said access transistor is connected to a wordline, and wherein the drain of said access transistor is connected to a first plate of said storage capacitor forming a storage node, and wherein the second plate of said storage capacitor is connected to a pump signal. This arrangement allows for a novel pixel circuit design with area requirements comparable to that of a 1T1C DRAM-like pixel cell, but with the advantage of an output voltage swing of the full range allowed by the breakdown voltage of the pass transistor. A spatial light modulator such as a micromirror array can comprise such a voltage storage cell.
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公开(公告)号：US06958846B2
公开(公告)日：2005-10-25
申请号：US10305507
申请日：2002-11-26
CPC分类号： B82Y30/00 , G02B26/0841 , H04N5/7458
摘要： A projection system, a spatial light modulator, and a method for forming micromirrors are disclosed. A substrate comprises circuitry and electrodes for electrostatically deflecting micromirror elements that are disposed within an array of such elements forming the spatial light modulator. In one embodiment, the substrate is a silicon substrate having circuitry and electrodes thereon for electrostatically actuating adjacent micromirror elements, and the substrate is fully or selectively covered with a light absorbing material.
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