公开(公告)号：US07383492B2

公开(公告)日：2008-06-03

申请号：US10392626

申请日：2003-03-20

申请人： Philip M. Sailer ,  Nicholas Paluzzi ,  Avinash Kallat ,  Stephen L. Scaringella ,  Krzysztof Dobecki

发明人： Philip M. Sailer ,  Nicholas Paluzzi ,  Avinash Kallat ,  Stephen L. Scaringella ,  Krzysztof Dobecki

IPC分类号： G06F11/00 ,  H03M13/00 ,  G11C29/00

CPC分类号： G06F11/1008 ,  H03M13/01 ,  H03M13/09

摘要： A system and method for determining data integrity as such data passes through a FIFO. A generator is provided for appending a bit in a predetermined bit location in each packet pushed into the FIFO in response clock signals. The appended bit is a function of the information pushed into the FIFO. A checker is provided for providing an indication of the information integrity in response to bits produced at an output of the FIFO in the predetermined bit location. In one embodiment, the generator is a parity generator and the checker is a parity checker. In one embodiment, during an initial test mode, one parity type is introduced into the FIFO by the parity generator and the opposite parity type is checked at the output of the FIFO by the parity checker to determine whether the parity checker is able to produce parity error signals. In another embodiment, the generator is a packet delimiter generator and the checker is a packet delimiter checker. In another embodiment, the generator is a frame delimiter generator and the checker is a frame delimiter checker.

摘要翻译： 用于当这些数据通过FIFO时确定数据完整性的系统和方法。 提供发生器用于在按照时钟信号被推入FIFO的每个分组中的一个预定比特位置中追加一位。 附加位是推送到FIFO中的信息的函数。 提供了一种检查器，用于响应于在预定比特位置中的FIFO的输出处产生的比特来提供信息完整性的指示。 在一个实施例中，发生器是奇偶校验发生器，并且检验器是奇偶校验器。 在一个实施例中，在初始测试模式期间，奇偶校验发生器将一个奇偶校验类型引入FIFO，并且在奇偶校验器的FIFO的输出处检查相反的奇偶校验类型，以确定奇偶检验器是否能够产生奇偶校验 错误信号。 在另一个实施例中，生成器是分组定界符生成器，​​并且检查器是分组定界符检查器。 在另一个实施例中，生成器是帧定界符生成器，​​并且检查器是帧分隔符检查器。

公开(公告)号：US07178000B1

公开(公告)日：2007-02-13

申请号：US10803377

申请日：2004-03-18

申请人： Krzysztof Dobecki

发明人： Krzysztof Dobecki

IPC分类号： G06F12/00

CPC分类号： G06F13/1689

摘要： A system for storing and retrieving data provided by the system on a system bus in a sequence at a predetermined system data rate. The system includes a system memory controller for enabling a system memory to store and retrieve the data at a rate twice the system data rate. Also provided is a trace buffer having a dual port random access memory. A trace buffer control system is provided for enabling the data on the system bus and fed concurrently to a pair of data ports of the dual port random access memory to be stored in the dual port random access memory at the predetermined system data rate and for enabling such dual port random access memory stored data to be retrieved from the dual port random access memory in the same sequence as such data was provided on the system data bus.

摘要翻译： 一种系统，用于按照预定的系统数据速率在系统总线上存储和检索由系统提供的数据。 该系统包括系统存储器控制器，用于使得系统存储器以系统数据速率的两倍的速率存储和检索数据。 还提供了具有双端口随机存取存储器的跟踪缓冲器。 提供了一种跟踪缓冲器控制系统，用于使得系统总线上的数据能够以预定的系统数据速率同时提供给双端口随机存取存储器的一对数据端口存储在双端口随机存取存储器中， 这样的双端口随机存取存储器将以与这些数据相同的顺序从双端口随机存取存储器检索的数据被提供在系统数据总线上。

公开(公告)号：US07107424B1

公开(公告)日：2006-09-12

申请号：US10809733

申请日：2004-03-25

申请人： Armen D. Avakian ,  Adam C. Peltz ,  Krzysztof Dobecki ,  Gregory S. Robidoux

发明人： Armen D. Avakian ,  Adam C. Peltz ,  Krzysztof Dobecki ,  Gregory S. Robidoux

IPC分类号： G06F13/00 ,  G06F13/43 ,  G11C7/00 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08

CPC分类号： G06F13/4243

摘要： A method for determining a read strobe pulse delay for data read from a memory having a plurality of memory chips. Each one of the chips provides data along with an associated read strobe pulse. The data read from each one of the plurality of chips is stored in a corresponding one of a plurality of storage devices in response to the read strobe pulse associated with such one of the plurality of chips. A training system determines a delay which when applied in to the plurality of read strobe pulses enables valid read data from the plurality of memory chips to be stored in each one of the plurality of the storage device in response to the read strobe pulses being delayed by the read pulse strobe delay. A process is used to enable preservation of the user data during the training process for use subsequent to the training process.

摘要翻译： 一种用于确定从具有多个存储器芯片的存储器读取的数据的读选通脉冲延迟的方法。 每个芯片都提供数据以及相关的读选通脉冲。 响应于与多个芯片中的一个芯片相关联的读选通脉冲，从多个芯片中的每一个读取的数据被存储在多个存储设备中的对应的一个中。 训练系统确定延迟，当应用于多个读取选通脉冲时，响应于读取的选通脉冲被延迟，多个存储器芯片中的有效读取数据被存储在多个存储器件的每一个中 读脉冲选通延时。 一个过程用于在训练过程中保持用户数据，以便在训练过程之后使用。

公开(公告)号：US06611879B1

公开(公告)日：2003-08-26

申请号：US09561161

申请日：2000-04-28

申请人： Krzysztof Dobecki

发明人： Krzysztof Dobecki

IPC分类号： G06F1300

CPC分类号： G06F3/0619 ,  G06F3/0656 ,  G06F3/0689 ,  G06F12/0866

摘要： A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives. The method includes transferring messages through a messaging network with the data being transferred between the host computer/server and the bank of disk drives through a cache memory, such message network being independent of the cache memory.

摘要翻译： 系统接口包括多个第一导向器，多个第二导向器，数据传输部分和消息网络。 数据传送部分包括高速缓冲存储器。 高速缓存存储器耦合到多个第一和第二导向器。 消息传递网络独立于数据传送部分运行，并且这样的网络耦合到多个第一董事和多个第二董事。 第一和第二位董事通过消息传递网络响应第一任董事和第二任董事之间的信息，控制第一任董事与第二任董事之间的数据转移，以促进第一任董事与第二任董事之间的数据转移。 数据通过数据传输部分的高速缓冲存储器。 一种用于操作适于在主计算机/服务器和一组磁盘驱动器之间传送数据的数据存储系统的方法。 该方法包括通过消息传递网络传送消息，数据通过高速缓冲存储器在主机计算机/服务器和磁盘驱动器组之间传输，这样的消息网络独立于高速缓冲存储器。